87C405AM

TMP87C405AM TOSHIBA | Alldatasheet

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• Manufacturer or author: TOLS
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@ 8-bit single chip microcomputer TLCS-870 series @ Minimum instruction execution time: 0.5 us (at 8 MHz, gear | SOP28-P-450-1.27 ratio 1/1) @ 129 types & 412 basic instructions ® Multiplication (8 bits x 8 bits, 16 bits +8 bits) : Execution time 3.5 us (at 8 MHz, gear ratio 1 1)) © Bit manipulations _——- (Set/ Clear / Complement/ Load / Store / Test / Exclusive or) @ 16-bit data operations @ 1-byte jump /call (Short relative jump / Vector call) 9 interrupt sources (External : 4, Internal : 5) @ Allsources have independent latches each, and nested interrupt control is available. © Edge-selectable external interrupts with noise reject - @ High-speed task switching by register bank changeover TMPB7CA05AM @ input / Output ports (22 pins) @ High current output : 6 pins (Typ.7 mA) @ Two 16-bit Timer/Counters ® Timer, Eventcounter, Programmable pulse generator output, Pulse width measurement, External trigger timer, Window modes Time Base Timer ® Interrupt frequency types : 8 types (1 to 16384 Hz) @ Divider output function (frequency : 4 types) @ Watchdog Timer @ Two Power saving operating modes @ STOP mode : Oscillation stops. Battery/Capacitor back-up Port output hold/high-impedance @ IDLEI mode : CPU stops, and Peripherals operate using high- frequency clock. Release by interrupts. MHz @ Emulation pod : BM87C408M0A geoe01c001 @ For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter . entitled Quality and Reliability Assurance / Handling Precautions. @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in’ which @ malfunction of failure of @ TOSHIBA product could cause loss of human Ive, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent ‘products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is resented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by Implication of otherwise under any. intellectual Property or other rights of TOSHIBA CORPORATION or others @ ihe information contained herein is subject to change without notice. 87C405A-1

TOSHIBA TENTATIVE TMP87C405A Pin Assignments (TOP VIEW) SOP28-P-450-1.27 xouTt <—-(1 28 )~— voo vest — 3 26 [1 ~= P10 (INTO) pe7 <> O14 25 [<> pit (INTs) pos «> (5 24 [<> P12 (INT2/TC1) (stops) p6s =~ C6 23 F< p13 (OVO) (stTop4) P64 <> (7 22 [1] <> P14 (PPG) (STOP3) P63 ~~» (8 21 D> p15 (TC2) p61 =~» 10 19 <> p17 (STOP/INTS) P76 ~<>(] 13 16 [<> p74 vss C14 15 OD ~<> p75 Block Diagram omer { yop Supply \\ vss ~ [tase [05] (=... Register Banks nace REEF system 1 TestPin TEST =o Program Memory ClockGear Timing Generator Time Base 16-bit _ Resonator iy Timer TimerrCounters conrectnag ound t | igh | coe Te | TSF ET O O O O Pe a 267 °17 °77 P66 ‘0 0 P6S (STOPS) P10 P72 to. to P62 (STOP2) be P60 (stop mode release) 87C405A-2

[rename | wewronee [mim id P17, PIG vO ‘B-bit programmable input/output P15(TC2) WO (Input) Each bit of the port can be individually Timer/Counter 2 input P14 (PPG) configured a3 en input or an output under | p-ogrammable pulse generator output prennnscrseemesne YQ (Output) _ | Sftware control. When used as an prmsetnninnnnnsrnaenensnnnnnrnecnsense P13 (BV) ‘external interrupt input or a timer Divider output PIT(INTI) VO (Input) output or a PPG output, the latch mustbe | external interrupt input 1 P10 (INTO) configured. External interrupt input 0 P67, P66 vo 8-bit programmable inpuvoutput port vnmsnsnsnsnunafusnonnnonosannn) i een, Buch Bit ofthe port ean be hana individually configured as an input or an P64 (STOPA) ‘output under software control. When Prveserereeeneerereen YQ (Input) used as stop mode release input, the PES (STORE) input modeis configured. P62 (STOP2) P61, P60 6-bit programmable input/output port P77 vo (tri-states). snmninnnminenefuenesnennneceseed Each bit of the port can be individually 76 (STOP/NTS) vo(inpu) —_| configured as an input or an output under | $10” mode relane inputfixternal interrupt S input P75t0 P72 vo When used as an external interrupt input, the input mode is configured. °. Resonator connecting pins for high-frequency clock. na Input, Ou i ‘ i IN, KOU Input, Output | Eos inputting external clock, XIN is used and XOUT is opened. esr | lw eset signal input or watchdog timer outpuvaddress-trap-reset output. Power supply 87C405A-3

1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer, This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 1.1. Memory Address Map The TLCS-870 Series is capable of addressing 64K bytes of memory. Figure 1-1 shows the memory address maps of the 87C405A. In the TLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the RAM address space. FR a SI pie 64 bytes ¢ Register banks i | 128 bytes } H ona [on] 7 (Breaistersx 16 banks) 0060 RAM! | aoa bytes Note; ROM; Read Only Memory includes : : Program memory o13F + J RAM; Random Access Memory includes : pd H Data memory is = Stack oro f 7 General- purpose register banks i SFR; Special Function Register includes : par| | | Bbytes WO ports i Peripheral hardware control registers OFF7 | 1 Peripheral hardware status registers 4 = ‘System control registers Pod i Interrupt control registers pi i Program Status Word Fooo C3g40 1 DBR; Data Buffer Register FOO ROM] i 192 iT ue Entry re for page HE vous [yeoman alinanction HDF jones | is vedon en interrupt vector tab seer 320 | Jerse B7CAOSA Figure 1-1. Memory address map a 87CASA-A

4.2. Program Memory (ROM) The 87C405A have a 4K bytes (addresses F000 to FFFFH) of program memory (mask programmed ROM). ‘Addresses FFO0 to FFF} of program memory is also used for a special purpose. (1) Interrupt vector table (addresses FFEO to FFFFH) This table consists of a reset vector and 16 interrupt vectors (2 bytes/vector). These vectors store reset start address and interrupt service routine entry addresses. (2) Vector table for vector call instructions (addresses FFCO to FFDF}) This table stores call vectors (subroutine entry address, 2 bytes/vector) for the vector calll instructions [CALLV a]. There are 16 vectors. The CALLV instruction increases memory efficiency when utilized for frequently used subroutine calls (called from 3 or more locations). (3) Entry area(addresses FFOO lo FFFFH) for page call instructions This is the subroutine entry address area for the page call instructions [CALLP a]. Addresses FF00 to FFBF} are normally used because addresses FFCO to FFFFH are used for the vector tables. Programs and fixed date are stored in the |*%re# ROM program memory. The instruction to be | F00 contents executed next Is read from the address |? | indicated by the current contents of the i Example: The relationship program counter (PC). There are relativejump |_| ee call and absolute jump instructions. The concepts | FFO0 group of page or bank boundaries are not usedinthe | instrucionsiterrupy program memory concerning any jump | : ‘eset instruction. i CALLP 7BH PC FF7Bq Example: The relationship between the | rar jump instructions and the PC. FFCO 56 CALLV OH ; PCeF8S6, © 5-bit PC-relative jump URS cc, $+2+d] | FFCt | Call vector(H) | F6 FEC4H: IRS T, $+2+08H FF When JF =1, the jump is made to F8CEH, | which is 084 added to the contents of the i . HOF PC. (The PC contains the address of the treo Interrupt vector()| 68 INTS + PC F368 instruction being executed +2; | prey limerupivecor ty] F3 therefore, in this case, the PC contents | gre, are F8CA) 4? = FACE) | | i i FFFD. @ 8&-bit PC-relative jump UR cc, $+2+d] fete. | UResetvector() | 32 reser | pce F035, FOCaH: JR 7, $42.4 80H sere [Reset vector (| 0 When 7F = 1, the jump is made to F846y, which is FF80}q (-128) added to the Figure 1-2. Program memory map current contents of the PC. @ 16-bit absolute jump [IP a] F8C4H: JP OF235H An unconditional jump is made to address F235y. The absolute jump instruction can jump anywhere within the entire 64K-bytes space. a 87CA0SA-5

In the TLCS-870 Series, the same instruction used to access the data memory is also used to read out fixed data stored in the program memory. The register offset PC-relative addressing (PC +A) instructions can also be used, and the code conversion, table look-up and n-way multiple jump processing can easily be programmed. Example 1 : Loads the ROM contents at the address spccified by the HL register pair contents into the accumulator (87C405 : HL 2 FOOOH) to A, (HL) i ASROM (HL) Fxample? : Converts BCD to 7-segment cade (common anode LED). When A = 08y, 92u is output to port P1 after executing the following program. ADD A, TABLE-$—4 } Pt <-ROM(TABLE +A) ' &h w (PN), (PC+A) t TABLE > DB OCOH, OFSH, OA4H, OBOH, 99H, 92H, 82H, OD8H, 80H, 98H d SNEXT: Notes: “$” isa header address of ADD instruction. DB is a byte data definition instruction. FP ecea) 4 Example 3 : N-way multiple jump in accordance with the contents of f=] accumulator (0 5 A $3). suc Lit Aco0y then rorrasay | S| P (PC+A) if A=O1y then PCHF378q if Az 02q then PCHFA37y + if A=03y then PCe-FIBOy ow 0F234H, OF378H, OFA37H, OF1BOH — Notes; _DWisa word data definition instruction. Word =2 bytes.

1.3 Program Counter (PC)

The program counter (PC) is a 16-bit register which indicates the program memory address where the instruction to be executed next is stored. After reset, the reset vector stored in the vector table (eddresses FFFFH and FFFE}) is loaded into the PG; therefore, program execution is possible from any desired address. For example, when FOq and 3Ey are stored at addresses FFFFH and FFE}, respectively, the execution sterts from address FO3E} after reset. The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always indicates 2 addresses in advance. For example, while a 1-byte Instruction stored at address F123y is being executed, the PC contains F125}. MSB se isaranw9s 876s 4azro — “omcrenter CX TX Xa) Program Counter (PC) (a) Configuration (b) Timing chart of PC counters and Instruction Execution Figure 1-3. Program counter a 87C405A-6

1.4 Data Memory (RAM)

The 87C405A has a 256 bytes (addresses 0040 to 013F}) of data memory (static RAM). Figure 1.4 shows the data memory map. Addresses 0000 to OOFFH are used as a direct addressing area to enhance instructions which utilize this addressing mode; therefore, addresses 0040 to OOFFy in the data memory can also be used for user flags or user counters. Example 1: If blt 2 at data memory address OOCOH Is “1”, OOH is written to data memory at address 00E3y; otherwise, FF} is written to the data memory at address 00E3y. ‘TEST (Q0COH).2 + if (00C04)2=0 then jump ARS T,SZERO CLR (Q0E3H) + (00E3,)e-004, ARS T,SNEXT SZERO: Lo (00E3H), OFFH 3 (Q0E3,)CFF Ey : ‘SNEXT: Example 2 : Increments the contents of data memory at address OOF5q, and clears to 004 when 10} is exceeded. INC (OOFSH) AND (QOFSH), OFH General-purpose register banks (8 registers x 16 banks) are also assigned to the 128 bytes of addresses 0040} to OOBFy. Access as data memory is still possible even when being used for registers. For example, when the contents of the data memory at address 0040} is read out, the contents of the accumulator in the bank 0 are also read out. The stack can be located anywhere within the data memory except the register bank area. For more details on the stack, see section “1.7 Stack and Stack Pointer”. With the TLCS-870 Series, programs in data memory cannot be executed. If the program counter indicates a specific data memory address (addresses 0040 to 013F}), an address-trap-reset is generated due to bus error. (Output from the RESET pin goes low.) The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example 1 : Clears RAM to 0 except the bank 0 Lo ‘HL, 0048H_ 7 Sets start address to HL register pair Lo AK j Setsinitial data (A) Lo Bc, OOF7H j Setsnumber of byte to BC register pair SRAMCLR: LD (HL +), A vec Be ARS F, SRAMCLR Note: “$" isa header address of ADD instruction. The general-purpose registers are mapped in the RAM; therefore, do not clear RAM at the current bank addresses. Clears RAM to 0 except the bank 0. ee — 87CQ05A-7

Address 0 1 2 3 45 6789 A8B CODE FP 00404 ~ RegigterbankO , Registerbank? meant pocbegagnartangg tb obongatrgaaparton oon Pega baa foo agigar panes wore Seabank piper ete aN i colinfdunteecterrtmbumnduenf | Directaddressing area 0030 :_ Regigterbank 10 ___fesigerbank tts ono | Register bank 12. «Register bank 13 0co Pbpb EEE EU: oro Pibipbip bi Ei pa Figure 1-4. Data memory map

4.5 General-purpose Register Banks

General-purpose registers are mapped into addresses 0040 to OOBFy in the data memory. There are 16 register banks, and each bank contains eight 8-bit registers W, A, 8, C, D, E, H, and L. Figure 1-5 shows the general-purpose register bank configuration. The unused register banks can be used as a data memory. | Bank 15 (0088 to 008F) : Bank 14 (0080 to 0087,) Example : Bank 0 - Rank 13 (OAR ta NOAF,,) Wo A wia Bank 12 (00A0 to 00A7y) ee sone ee o fonds) (ond>,) eee ee Bank 4 (0060 to 0067y) oe oe Rank 3 (O0SR to 008F,) (005) 00 enseeseeatfesesertes Bank 2 (0050 to 0057) i Hoi Bank 1 (0048 to 004F}) (0047) :(0046u) wank 0 (0040 10 00474) (2) Configuration ____(b) Address assignments of registers Figure 1-5. General-purpose register banks a 87C405A-8

In addition to access in 8-bit units, the registers can also be accessed in 16-bit units as the register pairs WA, BC, DE, and HL. Besides its function as a general-purpose register, the register also has the following functions. (1) A, WA The A register functions as an 8-bit accumulator and WA the register pair functions as a 16-bit accumulator (W is high byte and A is low byte). Registers other than A can also be used as accumulators for 8-bit operations. Examples: @ ADD AB j Adds 8 contents to A contents and stores the result into A. @ SUB WA, 1234H } Subtracts 1234y from WA contents and stores the result into WA. o sue EA } Subtracts A contents from & contents, and stores the result into E. (2) HL, DE The HL register functions as a data pointer/index register/base register, and the DE register pair function as a deta pointer to specify the memory address. HL also has an auto-post-increment and auto-pre-decrement functions. This function simplifies multiple digit data processing, software LIFO (last-in first-out) processing, etc. Example1: @ to A, (HL) {Loads the memory contante at the addrote specified by HLinto A. @ — LD_ A, (HL+52H) ~—;__ Loads the memory contents at the address specified by the value obtained by adding 52y te liLcontentsinto A. o@ Ww AHL+q) 1} Loads the memory contents at the address specified by the value obtained by adding the register C contents to HL contents Into. ® w A(HL+) j Loads the memory contents at the address specified by HLintoA. Then increments HL. © Ww A(-K) j Decrement HL. Then loads the memory contents at the address specified by new HL into A. TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This facilitates the programming of block processing. Example 2: Block transfer

10 Bm } man 1(n: Number of bytes to transfer)

Lo HL, DSTA Sets destination address Lo DE, SRCA + Setssource address SLOOP: LD (HU), (DE) i (HU) —(0E) Ine HL ; MLC HLS INC DE j DECDE+! ore 8 ; Beet IRS F, SLOOP j if BO then loop (3) B, C, BC Registers R and C can be used as 8-bit buffers or counter, and the BC register pair can be used as a 16- bit buffer or counter. The C register functions as an offset register for register offset index addressing (refer to example 1@ above) and as a divisor register for the division instruction Example 1 : Repeat processing 10. Bn } Sets nas the number of repetitions bec JRS F, SREPEAT Example 2 ; Division (16-bit +8-bit) DV WAC }_ Divides the WA contents by the C contents, places the quotient in A and the remainder in W. a 87CA05A9

The general-purpose banks are selected by the 4-bit register bank selector (RBS). During reset, the RBS is initialized to “0". The bank selected by the RBS is called the current bank. Together with the flag, the RBS is assigned to address 003F} in the SFR as the program status word (PSW). There are 3 instructions [LD RBS, n], [PUSH PSWJ, [POP PSW] to access the PSW. The PSW can be also operated by the memory access instruction. Example 1 : incrementing the RBS INC (003FH) =; RBSC-RBS +1 Example 2 : Reading the RBS LD A, (003FH) ; A«-RBS (The flags are simultaneously read in this instruction.) Highly efficient programming and high speed task switching are possible by using bank changeover to save registers during interrupt and to tronsfer parameters during subroutine processing. During interrupt, the RBS is automatically saved onto the stack. The bank used before the interrupt is automatically restored by executing an interrupt return instruction [RETIIRETN] ; therefore, there is no need for the RBS save/restore software processing. The TLCS-870 Series supports a maximum of 15 interrupt sources. One bank Is assigned to the main program, and one bank can be assigned to each source. Also, to increase the efficiency of data memory usage, assign the same bank to interrupt sources which are not nested. Example: Saving/restoring registers during interrupt task using bank changeover. PINTI: LD RBS, n } RBS <n (Bank changeover) RET! 1 Maskable interrupt return (Bank automatic restoring)

1.6 Program Status Word (PSW)

The program status word (PSW) consists of a register bank selector (RBS) and flags, and the PSW is assigned to address 003F} in the SFR. The RBS can be read and written using the memory access instruction, however the flags can only be read. When writing to the PSW, the change specified by the instruction is made without writing deta to the flags. For example, when the instruction [LD (003FH), 05H] is executed, “5” is written to the RBS and the JF isset to “1”, but the other flags are not affected. During interrupt, PSW is saved to the stack with the program counter. The PSWis restored from the stack by executing return instructions [RETIJ/[RETN]. [PUSH PSW] and [POP PSW] are the PSW access instructions. 1.6.1 Register bank selector (RBS) 7. 8 @3 2 10 The register bank selector (RBS) is a 4-bit register used to seiect oe bank 2 is currently selected. During reset, the RBS is initialized to “o". Figure 1-6. PSW (Flags, RBS) configuration a B7C405A-10

1.6.2 Flags (FLAG)

The flags are configured with the upper 4 bits : a zero flag, a carry flag, a half carry flag and a jump status flag. The flags are set or cleared under conditions specified by the instruction. These flags except the half carry flag are used as jump condition “cc” for conditional jump instructions [UR cc, $ + 2+ dl], [URS cc, $+2+d). After reset, the jump status flag is initialized to “1", other flags are nat affected. (1). Zero flag (2F) The ZF is set to “1” if the operation result or the transfer data is 00 (for 8-bit operations and data transfers)/0000} (for 16-bit operations); otherwise the ZF is cleared to “0”. During the bit manipulation instructions, the ZF is cleared to “0” if the contents of the specified bit is “1", This flag is set to “1” when the upper 8 bits of the product are 004 during the multiplication instruction, and when 00q for the remainder during the division instruction; otherwise it is cleared too" (2) Carry flag (CF) The CF is set to 1” when a carry occurred during addition or a borrow occurred during subtraction; otherwise the CF is cleared to “0”. During division. this flag is set to “1” when the divisor is 004 (divided by zero error), or when the quotient is 1004 or higher (quotiont-overflow error). The CF is also affected during the shift/ratate instructions. The data shifted aut from a register is set to the CF This flag is also a 1-bit register (a boolean accumulator) for the bit manipulation instructions. Set/clear/invert are possible with the CF manipulation instructions. Example: Bit manipulation (The result of exclusive-OR between bit 5 content af address 074 and bit 0 content of address 9Ay, is written to bit 2 of address 014.) to F, (0007H).5 4 (0001y)2 «(00071)5:v (009Ano XOR CF, (009AH) .0 10 (0001H).2, CF (3) Half carry flag (HF) The HF is set to “1” when a carry occurred to bit 4 of the operation result during an 8-bit addition, or when a borrow occurred from bit 4 of the result during an 8-bit subtraction. This flag is useful in the decimal adjustment for BCD operations (adjustments using the [DAA 1], or [DAS r] instructions). Example: 8CD operation (The A becomes 47} after executing the following program when A= 19, B= 28.) ADD AB > AGM, HFE1,CFe0 DAA A 7 ACA Iy + 064 = 47y (decimal-adjust (4) Jump stetus flag (JF) The JF is usually set to “1". Zero or carry information is set to the JF after operation. The JF provides the Jump condition for conditional jump instructions UR T/F, $+2=d}, URS TF, $ 424d] (TorFisa condition code). Example: Jump status flag and conditional jump instruction Inc A JRS T, SLABLEt ; Jump when a carry is caused by the immediately i preceding operation instruction. to A (HY), IRS T, SLABLE2 ; JFissetto "1" by the immediately preceding i instruction, making it an unconditional jump instruction. ‘87C405A-11

Example: The accumulator and flags becomes as shown below after executing the following instructions when the WA register pair, the HL register pair, the data memory at address 00C5, the carry flag and the half carry flag contents being “219Ay,", “00C5y", “D7,", "1", and “0”, respectively. ADE A, (HU n tioitia Ie A 9B oloitio suae A (HL) a2 |iioitio ROLC A a | tioitio cMP A, (HU wm |oioirio RORC A wo |oioioio AND A, (HU) 92 oloi1io app wa,orsoeH | t6az | 1:0: 1/0 to A, (HL) 07 tio: tio MUL W, A oa Jol oi1io AOD A, BH 00 riadada set AS. BA riaitio

1.7 Stack, Stack Pointer

1.7.1 Stack

The stack provides the area in which the return address or status, etc. are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt. On a subroutine call instruction [CALL a] / [CALLP a] / [CALLV n], the return address Is saved (the upper byte is pushed first, followed by the lower byte). During software interrupt instruction [SWI] execution or interrupt, the program status word is saved, then the return address is saved. When returning from the processing routine, executing a subroutine return instruction [RET] restores the contents to the PC from the stack; executing an interrupt return instruction (RETI] / [RETN] restores the contents to the PC and the PSW. The stack can be located anywhere within the data memory.

1.7.2 Stack pointer (SP)

The stack pointer (SP) is a 16-bit register to point out the first start address on the stack. The SP is post-decrement when a |" ee _ a m9 87 6S 439210 subroutine call or a push instruction is executed, or when an interrupt is accepted; and the SPC is pre-incremented when a tack Pointer (SF) return or a pop instruction is executed. The stack deepens to Figure 17. Stack pointer the direction of the lower address. Figure 1-8 shows the change of the stack access and the SP. The SP is not initialized hardware-wise but requires initialization by an initialize routine (sets the highest stack address). [LD SP, mn], [LD SP, gg] and [LO gg, SP] are the SP access instructions (mn; 16-bit immediate data, gg; register pair). Example 1 :To initialize the SP i>) ‘SP, 013FH 7 SPe-O13Fy Example 2 :TO read the SP Lo HL, SP 7 Hes ee 87C405A-12

At execution of or At execution of @CALUCALLW/CALLP—atexecution of Atexecution of @ ACTURETN instruction a SWI instruction a RET instruction instruction 0130 0130 | Pc, 0130 013 | Pa, O13E | PCL <tuen OTE | PCy “epee, OIE | PC be, O13E | PCy pte SA ess Reka ila means 0040, Eo | Stack i depth sp before [“013F O13Fn [01300] O13Cy i ? 1 y 1 t ener rekon 01364 O13 : : (a) Stacking order (b). Stack depth . Figure 1-8. Stack

1.8 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, a clock gear, and a stand-by controller. Clock gear control register Timing generator control register ti generator j 00304 | 53 [Loose XIN ut Page , ZN 4 High+trequency [!]"| clock gear Timing H H and-by controller o 4 clock oscillator | £ generator Stand-by controlie xourT bt : System elacke | fl 0038, 00394, Clock ganerator control System control registers Figure 1-9. System clock controller 87CA0SA-13

1.8.1 Clock generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. the high-frequency (fc) clocks can be easlly obtained by connecting a resonator between the XIN/XOUT pins. Clock input from an external oscillator is also possible. procacoeteaa""" High-frequency clock *-72=="""""2=~9 i XIN XOUT XIN XOUT i H Oo: | (open) | i Cl i H ! 1 (@) crystaliceramic (b) External oscillator | Figure 1-10. Example of resonator connection [Note: Accurate Adjustment of the Oscillation Frequency : Although no hardware to externally and directly monitor the basic clock pulse is provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulses ta the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand.

1.8.2 Clock gear

A clock generates the basic high-frequency clock which provides the system clocks supplied to the CPU core. The clock gear selects the high-frquency clock from fe, fe/2, fe/4 and fc/8. Power consumption can be redued by switching of the high-frequency from fc to £02, fc/4 and fu8. The clock gear consists of a divided-by-8 prescaler with a mutiplexer. Prescaler High frequency sawn — PE is mex Timing generator if 00030, Clock gear control register Note : MPX; Multiplexer Figure 1-11. Configuration of clock gear a R7CA05A-14

TOSHIBA TMP87C405A, (co0see) [regex] titiat value : 000+ 1000) FCGCK Gear clock selection (write) Ore* : reserved J gear clock monitor (read) 1000 : fe 1001 : fo2 1010 : fod 1011 :fy8 nw 1100 : reserved 111 reserved Note: fc; High-frequency clock *;don’tcare Note2: Bit 4 in CGCR is always read in as “1” when a read instruction is executed. Note3: Always set bit 7 to 5to “0” Figure 1-12. Clock gear control register CITT fos i A eek TULL 1. 1 r FCGCK H H H : 1000 : X 1011 i H Instruction execution Hi fegck= fe i Gearclock changing : fegck = fu8 Figure 1-13. Example of clock exchangeable timing by clock gear

1.8.3 Timing generator

The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions: ® Gencration of main system clock ® Generation of divider output (DVO) pulses @ Generation of source clocks for time base timer ® Generation of source clocks for watchdog timer © Generation of internal source clocks for timer/counters © Generation of warm-up clocks for releasing STOP mode (1) Configuration of timing generator The timing generator consists of a 21-stage divider with a divided-by-2 prescaler. During reset and at releasing STOP mode, the divider is cleared to “U0”, however; the prescaler is not cleared. Note : Even ifthe main system clock is changed by the clock gear, the output from the divider is not changed. The peripheral circuit using high-speed divider output (1st output) can not be used when the main system clock slows down. 87C405A-15

1.8.4 Stand-by controller

The stand-by controller starts and stops the oscillation circuits. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1.16 shows the operating mode transition diagram and Figure 1.1/ Shows the system control registers. (1) Operation mode The machine cycle time is 4/fcgck [s] @ NORMAL mode In this mode, both the CPU core and on-chip peripherals operate. The TMP87C408 is placed in this mode after reset. @ IDLE mode In this mode, the CPU and the watchdog timer are halted, however, on-chip peripherals remain active. IDLE mode is started by the system control register 2, and IDLE mode is released to NORMAL mode by an interrupt request from on-chip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is “1” (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is “0” (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction. @ STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. The output status of input output ports can be set to either output hold or high-impedance under software control STOP mode is started by the system control register 1, and STOP mode is released by STOP input pin (either level sensitive or edge sensitive can be selected). After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction. reset release instruction instruction IDLE mode NORMAL STOP mode Cc mode —__) interrupt Telease input Single Clock Mode Transition Diagram Operating | Oxxcillation cu core Machine eye mode circuit time [we | em turning on pom | halt T ff a Figure 1-16. Operating mode transition diagram R7C40SA.17

foosey (stor [mew [0 Jouren] wor] Gnitiat value: 0000 00+») mode: 0 : CPU core and peripherals remain active STOP [STOP mode start 1: CPU core and peripherals are halted RELM Release method for STOP 0: STOP pin input rising edge release mode 1: STOP pin input “H* level release couten | Port output control during 0: High-impedance STOP mode 1: Remain unchanged . 00: 3x2" /fe Warming-up time at or: fe wor releasing STOP mode 10: 3x2"/fe Ws 2" fe Note 1: Alwayssetbit sto "0". Note2: — Bits 1,0 in SYSCR1 is read in as undefined value when a read instruction is executed. Note3: fc ; clock [Hz] * ; don’t care Note4:; When the STOP mode is started by specifying OUTEN =“0“, the internal input of port is fixed to “0” and the interrupt of the falling edge may be set. System Control Reaister 2 High-frequency oscillator 0 : Turn off oscillation control 1 Turn on oscillation 0 : CPU, WDT operate Note 1: Avesetisopplied if XEN is cleared to "0", Note2: Alwaysset bit 6, 5to “0”. Note3: WDT; Watchdog timer, * ; don‘tcare Note4: — Bits 3 to 0 in SYSCR2 are read in as “1” when a read instruction is executed. Figure 1-17, System control registers 1,2 a 87C405A.18

1.8.5 Operating mode control

(1) STOP mode (STOP) STOP mode is controlled by the system control register 1 and the STOP pin input. The STOP pin is also used both as a port P76 and an INTS (external interrupt input 5) pin. The STOP mode is started by setting STOP (bit 7 in SYSCR1) to "1". During STOP mode, the following status is maintained. ® High-frequency oscillations are turned off, and all internal operations are halted. @ The data memory, registers (except for DBR), PSW, and port output latches are all held in the status in effect before STOP made was entered. The port output can select either output hold or high-impedance by setting OUTEN (bit 4 in SYSCR1). @ The divider of the timing generator is cleared to “0”. @ The program counter holds the address of the instruction after the following instruction which started the STOP mode. [for example, SET (SYSCR1)] STOP mode includes a level sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1). a. Level-sensitive release mode (RELM = 1) In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in STOP mode but instead will immediately start the release sequence (WARM-up). Thus, to confirm that the STOP pin input is low. The following method can be used for confirmation: Using an external interrupt input INTS (INTS is a falling edge-sensitive input). Example : Starting STOP mode with an INTS interrupt. PINTS: TEST —(P7).6 } To reject noise, the STOP mode does not startif ARS F, SINTS port P76 is at high. it) (SYSCR1), 010000008 j_ Sets up the level-sensitive release mode. ser (syscR1).7 7 Starts STOP mode Low (IQ, 1110011101010111B —;_ IL7, 5, 3-0 (clears interrupt latches) SINTS : RET! STOP pin \\ H Vow \\ xoutsin | | IM MIT NORMAL a STOP mode TF Warm-up > NORMAL operation operation Confirm by program that STOP mode is release by the hardware. the STOP pin inputis low ‘Always raloaced if the STOP and start STOP mode. (re inputis high. ) Figure 1-18. Level-sensitive release mode Note 1: After warm-up start, even IT STOP pin input Is fow again, STOP mode does nut restart. Note2: When changing to the level-sensitive release mode from the edge-sensitive release mode, the release mode is not switched until a rising edge of the STOP pin input is detected. a 87C405A-19

b. Edae-sensitive release mode (RELM = 0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is repeatedly executed at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high. Example: Starting STOP mode operation in the edge-sensitive release mode LD (SYSCR1), 000000008 1 OUTEN ¢-0 (specifies hiah-impedance) ol > IMFeo seT (SYSCR1). STOP } STOP «1 (activates STOP mode) Low GU, 1110011101010111B ; 1L7, 5,3 <0 (clears interrupt latches) El i IMFe1 . i\\ Vin \\ ‘STOP pin Hl 1 H Hi 1 i i NORMAL | NORM sTormede — +f< Worm up >} NORMAL sToPmede — STOP mode ttarted by the program. STOP mode is released by the hardware at the rising ‘edge of STOP pin input. Figure 1-19. Edge-sensitive release mode STOP mode is released by the following sequence: © The oscillator is turned on. @ Awarming-up period is inserted to allow oscillation time to stabilize. During warm-up, all internal operations remain halted. Four different warming-up times can be selected with WUT (bits 3 and 2 in SYSCR1) as determined by the resonator characteristics. @ When the warming-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. The start is made after the divider of the timing generator is cleared to "0". Table 1-2. Warming-up time example [yg renee 00 46.87 24.57 1 15.62 8.19 10 11.73 6.15 1" 391 2.05 Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore, the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value. STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. a 8B7C405A-20

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Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has heen connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (hysteresis input). (2) IDLE mode IDLE mode is controlled by the system control Y register 2 (SYSCR2) and maskable interrupts. The following status is maintained during IDLE mode. syinesruction @® Operation of the CPU and watchdog timer is halted. On-chip peripherals continue to operate. Yes @ The data memory, CPU registers, PSW, and Reset input. Reset port output latches are all held in the status in effect before IDLE mode was entered. No @ The program counter holds the address of No the instruction after the following Leverrupt reauest instruction which started IDLE mode. (Normal se) Tes Example: Starting IDLE mode. No meat SET (SYSCR2).4 IDLE mode includes a normal release mode and an es (interrups release mode) interrupt release mode. Selection is made with the Interrupt processing interrupt master enable flag (IMF). Releasing the IDLE mode returns ta NORMAL instruction which follows a. Normal release mode (IMF = "0") the IDLE mode start IDLE mode is released by any interrupt source instruction enabled by the individual interrupt enable flag v7 (EF) or an external interrupt 0 (INTO) request. Execution resumes with the instruction Figure 1-21. IDLE mode following the IDLE mode start instruction. The interrupt latches (IL) of the interrupt source used for release is required to be cleared to "0" by lvad instruction. b. Interrupt release mode (IMF = "1") IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 (INTO) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode. IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is started, the watchdog timer interrupt will be processed by IDLE mode will not be started. _ a 87CA05A-22

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4.9 Interrupt Controller

The 87C405A has a total of 9 interrupt sources: 4 externals and 5 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to “1” when an interrupt request is generated and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneoutly, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1-23 shows the interrupt controller. Table 1-3. Interrupt sources Interrupt vector Table] Interrupt Source EnableCondition | "vicn | adress | Priority ese [nominate [= [ert | ih a a skablt [eras [arc etter acon [wreteet | te | ree | | [exena [we —wtinwranen dees | ay | rm | | RESERVED RESERVED ay 87C405A-24

(1) Interrupt latches (IL15 to IL) Interrupt latches are provided for each source, except for a software interrupt. The latch is set to “1” when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to “0” just after the interrupt is accepted. All interrupt latches are initialized to “O” during reset. The interrupt latches are assigned to addresses 003C and 003DH in the SFR. Each latch can be cleared to "0" individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used (Do not clear IL2 for a watchdog timer interrupt to “0”). Thus, interrupt requests can be canceled and initialized by the program. Note that interrupt latches cannot be directly set to “1” by any instruction. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt requests by software is possible. Example 1 : Clears interrupt latches LDW (IL), 1111110100111111B j Ig to ILge-0 Example 2 : Reads interrupt latches LD WA, (IL) iWetly, ACL Example 3 : Tests an interrupt latch TEST = (IU).7 jILy=1 then jump JR F,SSET SSET: ie 87C405A-25

TosHBA_racaosn ATO TOTO TOTO TOTO TSH LEER LEL EEG eee Tel ee Ue Tel Ue ese ees | le hhh heheh h hhh hb dis CEES | if ALOR LLL gh 87C405A-26

(2) Interrupt enable register (EIR) The interrupt registers (EIR) enable and disable the acceptance of interrupts except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable interrupts cannot be nested more than once at the same time. The EIR consists of an interrupt master enable flag (IMF) and individual interrupt enable flags (EF). These registers are assigned to addresses 003Ay and 003Ry in the SFR, and can he read and written by an instruction (including read-modify-write instructions such as bit manipulation instructions). © Interrupt master enable flag (IMF) The interrupt master enable fiag (IMF) enables and disables the acceptance of all interrupts. Clearing this flag to “0” disables the acceptance of all maskable interrupts. Setting to “1” enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to “0” to temporarily disable the acceptance of maskable interrupts. Atter execution of the interrupt service program, this flag is set to “1" by the maskable interrupt return instruction [RET!] to again enable the acceptance of interrupts. If an interrupt request has already occurred, interrupt service starts immediately after execution of the [reti] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to “1” only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF =1). Note that IMF remains “0” when cleared in the interrupt service program The IMF is assigned to bit 0 at address 003Ay in the SFR, and can be read and written by an instruction. IMF is normally set and cleared by the [El] and [Dl] instructions, and the IMF is initialized to “0” during reset. @ Individual interrupt enable flags (EF15 to EF4) These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to “1” enables acceptance of an interrupt, setting the bit to “0” disables acceptance. Example 1: — Sets EF for individual interrupt enable, and sets IMF to "1" LOW (EIR), 1100000010100001B ; EF4s, EF14, EF7, EFs, IMFe-1 Example2: — Sets an individual interrupt enable flag to "1" . SET (EIRH).1 EFge1 Interruptiatch 151418210 St (003¢y, 003Dy) ae an TE. (00363) Interrupt enable register (Initial value: 00000000 000000+#) (o03a,, 0038, [sera OF OF oT 0 Tere t o [ery tere erg tere | TE ime) EIR, (003A, 1B (00381) cea aon. 00000000 0000**#0) Note 1: Donot use any read-modify-write instruction such as bit manipulation for clearing it. Note2: Donor clear the iL2 by en Instruction. Note3: Donot set IMF to “1” during non-maskable interrupt service programs. Fiqure 1-24. Interrupt latch (IL) and interrupt enable register (EIR) 87C405A-27

1.9.1 Interrupt sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “O" bya reset or an instruction. Interrupt acceptance sequence requires 8 machine cycles after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction (RETI] (for maskable interrupts or [RETN] (pseudo non-maskable interrupts). Figure 1- 25 shows the timing chart of interrupt acceptance and interrupt return instruction. (1)_Interrupt acceptance processing ® The Interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. @ The interrupt latch (IL) for the interrupt source accepted is cleared 0 “0”. @ The contents of the program counter and the program status word are saved (pushed) onto the stack. (pushed down in order of PSW, PCH, PC). The contents of Stack Pointer (SP) is decreased by 3. ® The entry address of the interrupt service program is read from the vector table address corresponding to the interrupt source, and the entry address is loaded to the program counter. © The instruction stored at the entry address of the interrupt service program is executed. Interrupt service task pce A sonal 7 j i tate H 7 ' H wr Hi } t ieseunie’Xeae YX rerreeerpienee REX) YX aerrertion execution) bg DCD CIID CCN, 3 CD (ED CHE) OD) TED CD CES) CES ° 2 KX XK FX) a Note: a;retum address b; entryaddress___c; address when the RET! instruction is stored Note2: The maximum response time from when an it ts set until an interrupt acceptance processing star(>is 3a/fegckls]. It equals to setting the IL on the first machine cycle in 10 cycles instruction execution. Figure 1-25. Timing chart of interrupt acceptance and interrupt return instruction Example: Correspondence between vector tale address for INTTBT and the entry address of the interrupt service program. Vector table address Entry address wim [Se am [Re FFF3y Fy F204, 064 ee 87C405A-28

A maskable interrupt is not accepted until the IMF is set to “1” even if a maskable interrupt of higher priority than that of the current interrupt interrupt being serviced. When nested interrupt service is necessary, the IMF is set to “1 in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. However, an acceptance of external interrupt 0 cannot be disabled by the EF, therefore, if disablement is necessary, either the external interrupt function must be disabled with the external interrupt control register (INTOEN) or interrupt processing must he avoided by the program. (When INTOEN =O, the interrupt latch IL3 is not set, therefore, the falling edge of the INTO pin input cannot be detected.) Example 1; Disables an external interrupt 0 using INTOEN: CLR (EINTCR). INTOEN ; INTOEN«0 Example 2 : Disables the processing of external interrupt 0 under the software control (using bit 0 at address OOFOH as the interrupt processing disable switch): PINTO: TEST (OOFOH).0 ; Returns without interrupt processing if (OOFOy)o = 1. IRS T, SINTO RETI RETI VINTO: DW PINTO (2)__General-purpose reaister save / restore processing During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but nat the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the came data memory area for saving ragisters. The following method is used to save / restore the general-purpose registers: @ General-purpose register save / restore by register bank changeover: General-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, benk 0 is used for the main task and banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RCTI] or [RETN]. Therefore, it is not necessary for a program to save the RBS. Example: Register Bank Changeover PINTXX: LD RBS, nj, Switches to bank n (1 ys at 8 MHz) _ Interrupt processing RET } Restores bank and Returns a 87C405A-29

@ General-purpose register save / restore using push and pop instructions: To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can he saved/restared using push/pop instructions. Example : Register save using push and pop instructions PINTxx ; PUSH WA ; Save WA register pair PUSH Hb esummnneg + Save HL register pair POP HL ; Restore HL register pair POP WA ; Restore WA register pair RETI ; Return Atacceptance of Atexecution of a push Avexecution of e pop At execution of an interrupt, an interrupt instruction of WA instruction of WA return instruction register reaister @ General-purpose registers save/restore using data transfer instruction: Data transfer instructions can be used to save only a specific general-purpose register during processing of a single interrupt. Example: Saving / Restoring registers hy data memary transfer instructions PINTxx: LD. (GSAVA), A. 7 Save Aregister 1_ Interrupt processing ._; Lo A, (GSAVA) ; Restore A register RET! > Return Main task Main task sank m (OtRRGROSR ORO Eb Apseptance Interrupt Wr LK, switch to bank n by \\ Saving Cf [LD RBS, n} instruction WS rcsistess “interrupt retur Restore bank | | m | Interrupt return automatically by \\ WKjrestoring ineerrape rs ASS Interrupt return: {a) Saving/ Restoring by register bank changeover {b) Saving / Restoring using push/pop transfer instructions Figure 1-26. Saving /restoring general-purpose registers en 87C405A-30

(3) Interrupt return The interrupt return instructions perform the following operations. {RETI] Maskable interrupt return [RETN] Non-maskable interrupt return ® The contents of the program counter and | @ The contents of the program counter and the program stetus word ere restored | program status word ere restored from . from the stack. thestack, @ The stack pointer is incremented 3 times. @ The stack pointer is incremented 3 times. © The imtersupt master enable flag is set to | @ The interrupt master enable flag is set to “ "1" only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remeins et “0* when so clear by en. interrupt service program. Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. (Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service is performed but not the main task.

1.9.2 Software interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Note: Software interrupt generates during non-maskable interrupt processing to use SWI Instruction for software break in a development tool. Use the [SWI] instruction only for detection of the address error of for debugging. © Address error detection FFy is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code FFy is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFu to unused areas of the program memory. Address-trap- reset is generated for instruction fetch from a part of RAM area (addresses 0040 to 013F}) or SFR area (0000 to 003F}) Note : The fetch data from addresses, BF80 to BFFF} for 87C405A and 87P808 is not “FF”, because the outgoing test ROM is contained. @ Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. a 87C405A-31

1.9.3 External interrupts

The 87C405A has four external interrupt inputs. Two of these are equipped with digital noise rejection cireuite(pulce inputs of less than a certain time are eliminated as noise) Edge selection is also possible with INT1, INT2 pin. The INTO / P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise rejection control and INTO / P10 pin function selection are performed by the ‘external interrupt control register. Table 1-4. External interrupts [source [vin | atttansh | crabiecondiions | tvge | vigtainesereiecioncreit_| Pulses of less then 15/fc or 63/fc{s) - are eliminated as noise. Pulses NTT (NTT Pi Falling edge equal to or more than 48/fc [s}] or or 192/fc [s] are regarded as signals. Balser of Tere than Wels] are Risingeage | Pulse ; . eliminated as noise. Pulses equal to wae Seagnaig 2A bl ore regarded assignals. SOF i eeget___| Fang Note 1 : The noise rejection function is also affected to detect the edge of Timer / Counter input (TCT pin). Note 2: The pulse width (both “H” and “L” level) for input to the INTO and INTS pins must be over 1 machine cycle. INTs tur toma > tye TR in Le Sis xto et NORMAL IDLE made Ptr tint : Note 3: If a noiseless signal is input to the external interrupt pin in the NORMAL or IDLE mode, the maximum time from the edge of input signal until the IL is set is as follows: @ INT1 pin 49/fc [5] (at INTINC = 1), 193/fc [s] (at INTINC =0) ® INT2 pin 25ite [s} Note 4: When INTOEN =0, the interrupt latch IL3 is not set even if the falling edge of INTO pin input is detected. Example ; Activating stop mode LD (SYSCR1), 010000008 ; OUTENc-0 (Specifies High-impedance) ol i IMFO SET (SYSCR1), STOP ; STOPe-t (Activates STOP mode) LOW (IL), 11111111010101118 = ;_-IL7, 5, 3€-0 (Clears interrupt latches) El } IMFe~1 a 87C405A-32

[ rine [inti nose reecttimessiect_| 0 : Pulses of less than 63/fc [s] are eliminated as noise INTINC JINTI noise rejecttimeselect | pulses of less than 15/fc [sre eliminated es noise INTOEN |PIO/INTOpinconfiguration | 4 iRTO pin (Port P10 should be set to an input mode.) INTZES | rt edge select 0: Rising edge INTL ES. VINNY ecige select 1: Falling edge Note: fe ; High-frequency clock [Hz] * 7 don't care Figure 1-27. External interrupt control register

1.10 Watchdog Timer (WDT)

The Watchdog Timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The Watchdag Timer signal far detecting malfunction can be selected either a reset output ara non- maskable interrupt request. However, selection is possible only once after reset. After reset, the signal is initialised to the reset output. When the Watchdog Timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. 87C405A-33

1.10.1 Watchdog timer configuration

a S| clock r Int rt t am [Sse yor fs Writing Writing worr r | disable code | clear code worour 0034, was] f WOTeR Watchdog Timer Control Registers Figure 1-28. Watchdog timer configuration 1.10.2 Watchdog timer contro! Figure 1-29 shows the Watchdog Timer control registers. The Watchdog Timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. © Setting the detection time, selecting output, and clearing the binary counter. @ Repeatedly clearing the binary counter within the setting detection time. If the CPU malfunction occurs for any cause, the Watchdog Timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTOUT = 1 a reset is generated, which drives the RESET pin to reset the internal hardware. When WDTOUT = 0, a Watchdog Timer interrupt (INTWDT) is generated. The Watchdog Timer temporarily stops counting in the STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP / IDLE mode is released. Example : Sets the Watchdog Timer detection time to 221/fc[s] and resets the CPU malfunction. Lb (worTcr2), 4EH j Clears the binary counters LD (WDTCR1), 000011018 =; WOTT<-10, WOTOUT<-1 Within 3/4 - LD (WOTCR2), 4EH } Clears the binary counters of WOT A (Always clear immediately after changing WOTT) detection i time E : LD (WDTCR2), 4EH } Clears the binary counters ‘Within 3/4 ! of WOT detection i time LD (WDTCR2), 4EH ; Clears the binary counters a 87C405A-34

Watchdoa Timer Control Reaister 1 NOON) Leeann aL WaT TEBE] Mtritiat value eee 1000 Watchdog timer enable / 0: Disable (itis necessary to write the disable code to WOTCR2.) WOTEN disable 1: Eneble 00: 25/fe [s} Watchdog timer detection | 01: 2° /fc write , WOT |time 10: Pfc only 11: 2/6 Watchdog timer output| 0: Interrupt request WOTOUT | erect 1; Reset output Note 1: — WDTOUT cannot be set to “1” by program after clearing WOTOUT to “0”. Note2: fc; High-frequency clock[Hz] *; don't care Note 3: — WDTCRI isa write-only register and must not be used with any of read-modify-write instructions. Note4: Disable the Watchdog Timer or clear the counter just before switching to STOP mode. When the counter is cleared just before switching to STOP mode, clear the counter again subsequently to releasing STOP mode. Watchdog Timer Control Register 2 7 6 5 4 3 2 1 0 Nossa ( ]_Mintintvate ese oeee) a 4Ey + Watchdog Timer binary counter clear , (clear code) er woter2 | Watchdog Timer control /ay, watchdog Timer disable ‘e code write register Castles) only Otners + lvalia Note 1: The disable code is invalid unless written when WDTEN -0. Note2: +; don’teare Note3: Since WDTCR2 is a write-only register, read-modify-write instructions (e.g., bit manipulating instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for read / write to this register. Note4: — Toclearbinary counter doesn't initialize the source clock, therefore, itis recommended to clear binary counter within 3/4 of the detection period. = Figure 1-29, Watchdog timer control registers (2) Watchdog timer enable The Watchdog Timer is enabled by setting WDTEN (bit 3 in WDTCR1). WDTEN is initialized to "1 during reset, so the Watchdog Timer operates immediately after reset is released. (3) Watchdog timer disable The Watchdog Timer is disabled by writing the disable code (B1}) to WDTCR2 after clearing WDTEN (bit 3 in WOTCRI1) to "0". The Watchdog Timer is not disabled if this procedure is reversed and the disable code is written ta WOTCR? before WOTEN is cleared to “0”. During disabling the Watchdoa Timer , the binary counters are cleared to “0”. Example: Disables Watchdog Timer . LDW (WDTCR1), 0B101H — ; WDTEN€-0, WDTCR2<-disable code Table 1-5. Watchdog timer detection time 09 4.194 o1 1.0485. 10 262.1 ins u 65.5ms a 87C405A-35

1.10.3 Watchdog timer interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. Ifa Watchdog Timer interrupt or a software interrupt is already accepted, however, the new Watchdog Timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the Watchdog Timer output as an interrupt source with WDTOUT. Example: Watchdog Timer interrupt setting up. LD SP, 013FH . ;- Setsthe stack pointer LD (WOTCR1), 000010008 +=; WDTOUT<0

1.10.4 Watchdog timer reset

If the Wetchdog Timer output becomes active, a reset is generated, which drives the RESET pin law to reset the internal hardware. The reset output time is 12/fcgck to 16/fegck [5] (1.5 to 2.0 ys at 8 MHz, 3.0 to 4.0 ps at 4 MHz, gear ratio 1/1). The RESET pin is sink open drain input/output with pull up resistor. 2c fa) : met Binary counter 1X__2__X3X 9 XX 2 XK Overflow i INTWOT Interrupt i WOT reset output rr ae Oi TTT TOO Tes outout) Writes 464 to WDTCR2 Figure 1-30. Watchdog timer interrupt / reset

1.11 Reset Circuit

87C405A has four types of reset generation procedures: an External reset input, an Address trap reset, a Watchdog Timer reset and a System clock reset. Table 1-6 shows on-chip hardware initialization by reset action. The internal source reset circuit (Watchdog Timer reset, Address trap reset, and System clock reset) is not initialized when power is turned on. Thus, output from the RESET pin may go low (maximum 16/fe[s] (2 ys at 8 MHz, 4 ys at 4 MHz). Table 1-6. On-chip hardware initialization by reset action [(——orechiptargware | _initatvaiwe | Onchiprerdwere [itis Velue | Program counter ceo | crrera-cerreyy | res<slerand Divider of Timing fo | generator Register bank selector (R85) 0 , Interrupt master enable flag (IMF) oO \\et of inputiout Refer to 1/0 port Interruptindividval enable flags (EF) ° Ouapus archer of inpuveuteut Por | rcuitry interrupt late wo control register revicters a 87C405A-36

1.11.1 External reset input

The RESET pin contains a hysteresis input with an internal pull-up resistor. When the RESET pin is held at low for at least 3 machine cycles (12/fcack Isl) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFE to FFF. vod Reset OF > Reset input Internal source <] a resp detain Figure 1-31. Reset circuit

1.11.2 Address trap reset

An Address trap reset is one of fail-safe function that detects CPU malfunction such as endless looping caused by noise or the like. If the CPU attempts to fetch an instruction from a part of RAM or SFR, an internal reset will be generated. Then, the RESET pin output will go low. The reset time is 12/fcgck to Instruction a a) {reset release _Xinsucvons r execution h — wenn nH Wd Addresstrapisocured == RESET output l ('U’ output) (Hi-2)} i H i H ! | 12Mfegek to 16/fegek [e] |! AMfegek to 16/fegek [e)] 1 16/fegck Is] | Nate 1: aisanaddressin on-chip RAM or SFR. Note2: During reset release, reset vector “r” is read out, and an instruction at address ris fetched and, decoded. Figure 1-32. Address trap reset

4.11.3 Watchdog timer reset

Refer to Section “1.6 Watchdog Timer”. 1.11.4 System clock reset . Clearing XEN to “0" stops a system clock, and causes CPU to deadlock. This can he prevented by automatically generating a reset signal whenever XEN =0 is detected to continue the oscillation. Then the RESET pin output goes low . The reset time is 12/fegck to 16/fegck [2] (1.5 4 ~ 2.0 us at MHz, 3.0 to 4.0 ys at 4MH2). eS 87C405A-37

1. On-chip Peripherals Functions

2.1 Special function register (SFR)

The TLCS-870 Series uses the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function registers (SFR) . The SFR are mapped to addresses 0000 to 003F}. Figure 2-1 shows the 87C405 SFR. [Address Read Write ‘Address Read Write LL) ee —_ | 01 Par cccecssseensecesseneescetsent SPOR seeguseeaeensesetneeieese QD Yaceccenseessesnseeesseseseresee AGREED ssseensetnsennseetsseeesete 02 seeenneserees esse TASES sceeneeneetnnnnnnnstnnne 22 Yaresssssessssessneessseseesser AOIRIYES, sseuneenneemnseenssesneesie [Ss nS 7 O(n CY 1, On en nn ee ne: ne | Cs a” ee | OB Joon cccssseneeseneensntasneeefe SOREL POU Crt. BB JacessnseseccsesenssnsrvnessennnessnnesSennseennsecsenaseseesoannncenessetcual Oe oon ceseneeneef OCR IPE POREUO COMO... | LE | acaseenteernteneeseenensesensfiensnnenatvenssunerneenessesee Cs nn a 225.6020 a a! OE fac csseerneneseensent SEES. cssensseeeenessvaeenenene] RE Leassenerneereerserserntnrntserncnsetseransaensnnsenaenansene oF econ Fis srapew hey Wakeup control 10 Pos ccesessnen Tvenensenesnssef REGIAY, a 1A) BO Passensesserensseresss GER ISIE ROE SNMEOM.sscseessenesseessesrny 16 = RECA mor register Fe ooeeceee nn cTATCRTBTITS 10VO cont) cnn nn. nnn ME A et | Te oon aesenentmnsnrseene at OATUOG, sareseeeenenestentnsstn BB | a asseneseeneenr SYSERY stem control) srrerreseesevnesel

13 III) ag [ease omen |

£7 Ss nn en E78 Henne serruptenable regi oo] ie a eS nc | iF a ar [eSw Ras igi bank wlecion) (2) Special Function Register Note1: Do not access reserved areas by the program. Notez: = ; cannot be accessed. Note3: When defining address 003F with assembler symbols, use GPSW and GRBS. Note4: Write-only registers and interrupt fatches cannot use the read-modity- write instructions (bit manipulation instructions such as SET. CLR. etc. and logical operation instructions such as AND, OR, etc.) Noted: FSW; Program Status Word Figure 2-1. SFR eo 87C405A-38

2.2 VO Ports

The 87C405A has 3 ports, 22 pin input/output ports. © Piport ;8-bit/O port (External interrupt input, Timer/Counter input/output, and Divider output) @ Péport ;8-bit!/O port (STOP mode release input) @ P7port ;6-bit/O port (External interrupt and Timer/Counter input / output) Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2-2 shows input/output timing examples. External data is read from an 1/0 port in the S1 state of the read cycle during execution of the read Instruction. This timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. Output data output changes in the S2 state of the write cycle during execution of the instruction which writes to an /O port. fetcheycle | fetcheycle read cycle $0 1 52 $9 50 $1 52 59 50 51 52 53 executiongyde === — Data input 1 ZZZZZE-LLLLLLLLLLL XL... (a) Input Timing fetcheycle_._ fetcheycle write cycle SO S1 S2 S3 SO St S2 $3 SO S1 S2 S32 Data output a x mr (b) Output timing Note : The positions of the read an write cycles may vary, depending on the instruction. Figure 2-2. Input/output timing (Example) When reading an VO port except programmable /O ports, whether the pin input data or the output latch contents are read depends on the instructions, as shown below : (1) Instructions that read the output latch contents @ XCH F, (sre) ® LD (pp).b,CF @ SET/CLR/CPL (src).b © ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), n @ SET/CLR/CPL (pp).g —D (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) @ LD (src).b, CF (2) Instructions that read the pin input data Instructions other than the above (1) and (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (scr), (HL) 87C405A-39

2.2.1 Port P1(P17 to P10). Port P1 is an 8-bit input/output port which can be configured as an input or an output in on-bit unit. Input / output made is specified by the port P1 input/output control register (P1CR). During reset, the PICRis initialized to “0”, which configures port P1 as an input. The P1 output latches are also initialized to “0” Port Pt is also used as an External interrupt input, a Timer / Counter input, and a Divider output. When used as secondary function pin, the input pins should be set to the input mode, and the output pins should be sct to the output mode and beforchand the output latch should be set to “1”. Itisrecommended that pins P11 and P12 should be used as External interrupt inputs, Timer/ Counter Input, or Input ports. The interrupt latch is set at the rising or falling edge of the output when used as output ports. Pin 10 can be configured as either an input / output ports with INTOEN or an External interrupt input. During reset, pin P10 is configured as an input port. stop ° OUTEN 1 > D> nen pT | Data input EB << Dataoutput —>f> a] . tL rc output latch Pu Control output fon Note: i=7to0 PI P17 : Pie | pis; Pia Pia ipat pripio | (00014) H E Tea | PPG! DVO Tet | INTH ! INTO | (Initial value: 0000 0000) pe, CE trates 00 000 (0008H) WO control for port Pt 0: Input mode write (specified in one-bit unit) 1: Output mode only Note: P1CRisa write-only reaister and cannot be used by any read-moddify-write instructions. Figure 2-3. Port 1 and PICR Example: Sets P17, P16 and P14.as output ports, P13 and P11 as input ports, and the others as function pins. internal output data is “1" for the P17 and P14 pins, and “0” for the P16 pin. LD (EINTCR), 010000008 INTOENE@1 Lo (P1), 101111118 } PI7E4, P1det, P16HO LO (P1CR), 110100008 Note : Ports set to the input mode read the pin states. When input pin and output in exist in port PT together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to output mode read a value of the output latch. aE 87C405A-40

2.2.2 Port P6 (P67 to P60)

Port P6 is an 8-bit general-purpose input/output port which can be configured as an input or an output in one-bit unit. P62 to P65 are used as key wake-up inputs. Input / output mode is specified by port P6 input/output control register (PECR) . During reset, P6CR is set to “0”, port P6 is in input mode. During reset, the output latches of port P6 is initialized ta “0”. PGCR is write-only register. In the case af using port P6 as key wake-up inputs, please refer to Section "2.11 Key wake up". stor OUTEN {> PECRI - 7 — a Data output P 2 | {> [_] Psivi=ot071 Output latch Key wake-up input oH Pek k= 2105) er oe Wy | P67 : PEG: POS { PO4 ; POS: PO2 | PET | POO | ‘initial value 0000 0000) i [STOPS !STOP4 : STOP3 :STOP2 : i P6CR 7 6 5 4 3 2 4 0 (000) [7 (initial value 0000 0000) VO control for port PE 0: ingutmode (cpocified in one-bitunit) | 1 : Outputmede Note! : Used anzleg input pins or key wake-up input must be configured as input made ‘Note2 : The P6CR is @ write-only register and cannot be used by any read-modify instructions. Figure 2-4. Port P6 and PECR Note : Ports set to the input mode read the pin states. When input pin and output in exist in port P1 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to autput made read a value of the output latch. 87C405A-41

2.2.3 Port P7 (P77 to P72)

Port P7 isa 6-bit general-purpose input / output port which can be configured as either input or output in one-bit unit. Input / output mode is specified by port 7 input / output control register 1 (P7CR1). Input/output circuit is specified by port 7 input / output control register 2 (P7CR2). During reset, P7CR1 is cleared to “0”, and port P7 is configured as an input mode. The output latches are initialized to “0”. P7CR1 is write-only register. P76 is also used as an External interrupt input or as a STOP mode release input. STOP es —s D i ouetnps a Data output fp 2 | » | [] P7ii=2t0 7) Control input o€ P76 (INTS/STOP) P7 7 6 5 4 3 2 1 ~O (0007) [p77 1P76 P75 i p74ip73ipZ: i storie EE Pints: if EEE {Initial value 0000 00*#) port) 7 6 5 4 3 2 1 0 prcr1 | YOcontrol for P7 0: Input mode CRI | specified in one-bit unit) 1: Output mode pore 7 6 5 4 3 2 1 OO prep? | YOcontrol for P7 0: Open drain input / output (specified in one-pit unity 1: Tristate input/output Note: The P7CRis a write-only register and cannot be used by any read-modify instructions. Figure 2-5. Port P7 and P7CR Note 1: , Ports set to the input mode read the pin states. When input pin and output in exist in port P7 together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to output mode read a value of the output latch. INote 2: In case of using P62 to P65 as key wake-up inputs, use P76 (including INTS/STOP) only as an input, do not set it as output. INote3:_* ; Don‘tcare Example : The lower 2-bit of Port P7 is set to an output port and the others are set to an input port. LD (P7CR1), OFH i P7CR1<-00001111 a 87C405A-42

2.3 Time Base Timer (TBT) _

The Time-base timer is used to generate the fe 223 base time for key scan and dynamic display fe 3 ssing. For this purpose, it generates fers 7 [Beuee processing. purpose, it g a fe/2"4 w [clock Rising INTTBT time-base timer interrupt (INTTDT) at te2? 4 TY edge f> interrupt predetermined intervals. fe2? ° detector} request . This interrupts generated beginning with hae “ the first rising edge of the source clock (the timing generator’s divider output selected retek TBTEN by TBTCK) after the time-base timer is enabled. Note that since the divider cannot i ~ i a Time Base Timer Control Register be cleared by a program, the first interrupt te). Contiguratian only may occur earlier than the set ource clock interrupt period. (See Figure 2-6, (b).) eee J I When selecting the interrupt frequency, | BTEN - - ~ make sure the time-hase timer igdisabled. |""* H i i (Do not change the selected interrupt — Pood F t frequency when disabling the active timer oe | ee | rs either.) However, you can select the Enable rar terupt period . interrupt frequency simultaneously when . oe enabling the timer, (b) Time base timer interrupt Figure 2-6. Time bese timer 7 6 5 4 3 2 1 0 toe [leveoa] wovgeo | 0 | raven TOTCK , (initial value: O##0 Owe) Time Base Timer 0: Disable 000: fc/2?3 [Hz] 003 : fe/22! 010 : fe/2'6 Time bate timerinterrupt | 011: fe/ 214 TBTCK | srequency select 400 : fc/2"3 101: fes2"? 110; tes2"* 114: fos 28 Note1: fc; clock [Hz], * ; don’tcare Note2: _ The fourth bit in TBTCR must be to "0". Figure 2-7. Time base timer control register Table 2-1. Time base timer interrupt frequency [Hz] 000 0.95 oo 3.81 010 122.07 on 488.28 100 976.56 101 1953.12 110 3906.25 mW 15625 a 87C405A-43,

2.4 Divider Output (DVO)

50% duty pulse can be output using the Divider output circuit, which is useful for piezo-electric buzzer drive. Divider output is from pin P13 (DVO). The P13 output latch should be set ta “1” and then the P13 should be configured as an output mode. 7,6 5 4 3 2 1 ~«O feos (evoen[ovgce [0 [owen | rarex, ]—_tinitiat value: +40 +e) DVOEN | Divider outputenable/disable| + Disable 1: Enable 00: fe/2"3 {Hz} Divider output (DVO pin) Ol: fe/2'? PVOCK | frequency selection 10: fe/2" 14: fes20 Note: fe; High-frequency clock [Hz], * ; don't care Figure 2-8. Divider output control register Example: 1 kHz pulse output (at fc=8 MHz) set ens 3 P13 outputlatch 1 to (P1cR), 000010008 7 Configures P13.s.an output mode wo (TaTcR), 100000008 j DVOEN€+1, DVOCKe-00 Table 2-2. Frequency of divider output [kHz] 00 ost2 0.976 o1 1.024 1.953 10 2.008 3.906 " 4,096 7812 Outputlatch Output mode (P1CRs) Output data—>[>_ 2} Da BE) Selector {1213 Ja fes2" KY P13 output latch. fk, output taten_f LJ Dvock DVOEN DVOEN — } OL Divider output control recister DVO pin - (2) Configuration (b) Timing Chart Figure 2-9. Divider output 87C405A-44

2.5 16-bit Timer/Counter 1 (TC1)

2.5.1 Configuration

A pols Fa i . He ° #13 zz ri a Pa mE é A 3 8 A (_) * iz ze CR: | Lat i. aee a 87C405A-45 .

2.5.2 Control

The Timer/Counter 1 is controlled by a Timer/Counter 1 control register (TC1CR) and two 16-bit timer registers (TREG1A and TREG1B). Timerregixer 15 1413 12,1109 Toros tore TREGIAy (0011) REGIA, (0010) rReG1B Write only Torn 0013.9) TREGIBy (OO) ss, gy FREGTB, (00124) Timer/Counter Read / Write (Write available in only PPG output mode) 7 6 5 4 3 2 al oO Scart ws, FFT Mert Tes TCICK TCIM (initial value : 0000 0000) 00 : Timer / External trigger timer / Event counter mode grein TC! 01: Window mode mode select, 10 ; Pulse width measurement mode 11 : PPG (Programmable pulse generate) output mode 00: Internal clock = fc/2" = [Hz] resce JTC Ot: Internal clock fe/2” 7 source clock select, 10: Imternal clock fer2? 11: External clock (TC1 pin input) 00 : Stop & counter clear gers TCH 01: Command start - start control 10; reserved 11 : External trigger start Pulse width meas t MET External ‘trigger timer 0: Triggerstart 1: Triggerstart & stop a ncaa Note 1: fe: High-frequency clock [Hz] Note2: Writing to the low-byte of the timer registers (TREG1A,, TREG1By, the comparison is inhibited until the high-byte (TREG1Ay, TREG1By) is written. (Only the low-byte of the timer registers cannot be changed.) After writing to the high-byte, the comparison within 1 cycle(during instruction execution) is ignored. Note3; Set the mode, source clock, edge (INTZES), PPG output contro! and timer FIFI control when TC1 stops (IC15 = 00). Note4: Software capture can be used in only timer and event counter modes. SCAPI is automatically cleared to "0" efter software capture. Note5: Values to be loaded to timer registers must satisfy the following condition. TREG1A>TREGIB>0 (PPG output made); TREG1A>0 (except for PPG output mode) Note 6: Always write “0” to TFF1 except the PPG output mode. Note 7: TREG1B canbe written only in PPG outout mode. Note8: TCICR is a write-only register, which cannot be accessed by any read-modify-write instructions such as bit operate, etc. Note 9: When f!23 is selected as a source clock in the pulse width measurement mode, the lowest bit (bit0) of the counter value (TREGIB) is always read in as "0". When others are selected as a source clack, the counter value is read according to the count. Figure 2-11. Timer registers and control register TC1 87C405A-46

2.5.3 Function

Timer/Counter 1 has six operating modes: Timer, External trigger timer, Event counter, Window, Pulse width measurement, and Programmable pulse generator output mode. (1) Timer mode In this mode, counting up is performed using the internal clock. The contents of the Timer register 1A (TREG1A) are compared with the contents of up-counter. If a match is fund, an INTTC1 interrupt is generated, and the counter is cleared to "0". Counting up resumes after the counter is cleared. The current contents of up-counter can be transferred to the Timer register 1B (TREG1B) by setting SCAP1(bit 6 in TC1CR) to “1” (software capture function). SCAP1 is automatically cleared to “O" after capturing. Table 2-3. Timer/counter 1 source clock (internal clock) (at fc = 8MHz) [rere Resolution tis] | _Maximumumeseningis|_ 00 256 16.8 on 16 1.0 10 1 65.5 m Example 1 : Sets the Timer mode with source clock f¢/211[Hz] and generates an interrupt 1s. later (at f¢ = 8 MHz). Low (TREG1A), 10004 + Sete the timar register (164.211 /fe = 1000,,) Set (EIRL). EFA ; Enables INTTC1 interrupt Lo (TC1CR), 000100008 j Starts TC1 \\Note: TCICRis a write-only register, which cannot start by [SET(TC1CR).4] instruction. Example 2 : Software capture LD (TC1ICR) , 010100008 1 SCAPIO-T Lo WA, (TREG1B) ; Reads captured value ‘Command start Source clock 1 counter n 7X2 YXEXD) XM OOOAAIDEX Timerregister tA XA

1 Match ‘Counter:

INTTC1 interrupt i detect clear {a) Timer mode Source clock Timer register 18 7 (eX seam i f (b) Software Capture Figure 2-12. Timer mode timing chart B7C4A05A-47

(2). External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the riging or the falling edge can be selected. Edge selection is the same as for INT2 pin. Source clock is used an internal clock selected. The contents of TREG1A is compared with the contents of up-counter. If a match is found. an INTTC1 interrupt is generated, and the counter is cleared to “0” and halted. The counter is restarted by the selected edge of the TC1 pin input. When the edge input is opposite to the edge input way of the count start trigger at METTI (bit 6 in TC1CR) = 1, the counter is cleared, and count stops. In this mode, pulse input with a constant pulse width generates interrupt. When METT1 is “0", the opposite edge input is ignored. The edge of TC1 pin input before match detection is also ignored. The TC1 pin input has the same noise rejection as the INT2 pin, therefore, pulses of 7/fc [s] or less are rejected as noise in NORMAL or IDLE mode. A pulse width of 24/fc [s] or more is required for edge detection. Example 1 :Generates interrupt after 100 4s from TC1 pin input rising edge (at fc = 8 MHz). Lo (EINTCR), 000000008 } INT2ES€-0 (rising edge) LOW (TREG1A), 0064H 7 100s +23/fc=64y ‘SET (EIRL).EF4 ; Enables INTTC1 interrupt a to «TCICR), 001110008 } Starts TC! external trigger, METT = 0 Example 2 : When “L” level pulses of 4ms or more is input to TC1 pin. generates interrupt. {at fc= 8 MHz) io (eINTeR), onn00100R 2 INTIFSE (falling edge) Low (TREG1A), OOFAH 3 4ms+27/ fc Fay set (EIRL).EF4 4 Enables INTTC1 interrupt el wo (TCICR), 011101008 j_ Starts TC1 extemal trigger, METT=1 Count start Count start Rising edge ni i Tri f select ‘TC1 pininput } igger Trigger (INT2ES = 0) Internal clock i I | | Timerregister 1A “7 Xa - Match (4) clear INTTC1 interrupt (a) Trigger Start (METT1 =0) Count Count Count =n ear = Rising edge select TC1 pininput j Trigger 1 Trigger i Trigger Y (ntes=0) Internal clock L i Counter 2 ONG KEK TOG RIES, Note: m<n Timerregister 14 Xa Match U Joear INTTC1 interrupt (b)_Trigaer Start & Stop (METT1 = t) Figure 2-13, External trigger timer mode timing chart a 87CA05A-48

(5) Pulse width measurement mode Counting is started by a trigger of the rising (falling) edge of the 1C1 pin input (set to external trigger start by TC1CR). The source clock is used an internal clock. On the next falling (rising) edge, the counter contents are transferred to TREG18 and an interrupt is generated. The counter is cleared when the single edge capture mode is set. When double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to TREG1B. If a fallina (rising) edge capture value is required, it is necessary to read out TREG1B contents until a rising (falling) edge is detected. Falling or rising edge is selected with INT2ES, and single edge or double edge is selected with MCAP1 (bit 6 in TC1CR). Example : Duty measurement (Resolution fe/27[H2]) CLR (INTTCISW).0 ;_ INTTC! service switch initial setting > {EINTCR),000000008 -;_ Setsthe rising edge et the INT2CS edge fa) (TC1CR), 000001108 3 Sets the TC1 mode and source clock ‘SET (EIRL). EF a i Enables INTTCI el LD (TCICR), 001101108 3 Starts TC1 with an external trigger in MCAPT =0 PINTTCI: CPL (INTTCISW).0 ; Complements INTTC1 service switch IRS F,SINTTCI wo (HPULSE),(TREGIBL) ;_-Reads TREGIB to (HPULSE + 1), (TREG1BH) RETI SINTTCI = iD (WIDTH), (TREG1BL) : Reads TREG1B (Period) Lo (WIDTH + 1), (TREGIBH) i + Dutyealeulation RET VINTTC1 : DW PINTTC1 k WIDTH i EHPULSE fi ee a a INTTCISW a rs Note: When 0/23 is selected as a source clock in the pulse width measurement mode, the lowest bit (bitO) of the counter value (TREGIB) is always read in as "0". When others are selected as a source clock, the counter value is read according to the count. a 87C405A-50

TC! pin input Mviieser Y I (INT2ES = 0) Internal clock l j ] Counter CD ED ED ED €D Gd > GE ED GEE) ©) ?\\ Capture TREGIS 7 INTTC1 interrupt ] [Application] High or low pulse width measurement (@)_ Single edge capture (MCAP = 1) Count start Count start TCt pininput rs ee Internal clock H LI Counter SX EXE KEK EX HK KKK NIE X 2 TREGIB (co Or INTTC1 interrupt [Application] © Period/Frequency measurement @ Duty measurement (b) Double edge capture (MCAP1 = 0) Figure 2-16. Pulse width measurement mode (6) Programmable pulse generate (PPG) output mode Counting is started by an edge of the TC1 pin input (either the rising or falling edge can be selected) or by a command. Edge select is the same as for INT2 pin. The source clock is used an internal clock. First, the contents of TREG1B are compared with the contents of the up-counter. If a match is found, Timer F/F1 output is toggled. INTTC1 interrupt is generated at continuous output (MPPG1 =0) Next, Timer F/F1 is again toggled and the counter is cleared by matching with TREGIA. An INTTC1 interrupt is generated at this time. Timer F/F1 output is connected to the P14 (PPG) pin. In the case of PPG output, set the P14 output latch to “1” and configure as an output mode. Timer F/F1 is cleared to “0" during reset. The Timer F/F1 value can also he set by TFF1 (bit 7 in TC1CR) and either a positive or negative logic pulse output is available. Also, writing to the TREG1B is not possible unless the Timer/Counter 1 is set to the PPG output mode. Example ; “H” level 800 ys, “L"” level 200 us pulse output at fe = 8 MHz ‘SET (P1).4 ; P14outputlatche1 LD (PICR), vo0I0008-—;_Sets P14 toan output mode LO (TCICR), 100010118; Sets PPG output mode LOW (TREGIA), O3ESH j Setsa period (1 ms+ 1 ys=0368y) LOW (TREG1B), 00CBH Sets “L” level pulse width (200 ps + 1 4s = 00CB,) LD (TC1CR), 100100118 ; Start 87C405A-51

2.6 16-bit Timer/Counter 2 (TC2)

2.6.1 Configuration

teas [> Tce2pin O lH wet V Soon 8 fa. | Yio 16-bit up-counter E etch tow comparatog > 2e8et InTTC2 B » interrupt Teck Teas [- Enable TC2CR TREG2 Timer/Counter 2 control register 16-bit timer register 2 TREG2H ‘TREG2L write strobe. Figure 2-19. Timer/counter 2 (TC2)

2.6.2 Control

The Timer/Counter 2 is controlled by a Timer/Counter 2 control register (TC2CR) and a 16-bit timer register 2 (TREG2). qae@2 is 3 1 OS UO wite only Te2cr eee coo 6 5 4 3 2 1 0 tom | Timer/Counter 2 operating 0: Timer/Event counter mode mode select 1: Window mode 000 : Internal ciock fe /2#®_ [Hz] 01: Internal clock fe 010 : Internal clock fe/2" inter 2 D reac | TimeriCounter2 O11 :Internal clock ——_fe/2? write 100 : reserved only 101 : reserved 110 ; reserved 111: External clock (TC2 pin input) teas _| Timer/Counter 2 0: Stop and counter clear start control 1: Start Note 1: fe; High-frequency clock [Hz], *; don't care Note2: When writing to the low byte of timer register 2 (TREG2,), the comparicon it inhibited until the high-byte (TREG2,) is written. After writing to the high byte, any match during 1 machine eyele (instruction execution cycle) is ignored. Note2: Set the mode and source clock when TimerlCounter stops (TC2S =0). Note 4: Values to be loaded to the timer register must satisfy the following condition. TREG2 > 0 Note 5: TC2CR is a write-only register and cannot be used with any of the read-modify-write instructions. Figure 2-20. Timer register 2 and TC2 control register 87C405A-53

2.6.3 Function

The Timer/Counter 2 has three operating modes: Timer, Event counter and Window modes. (1) Timer mode In thie mode, the internal clock is used for counting up. The contents of TREG2 are compared with the contents of up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Table 2-4. Source clock (internal Clock) for timer/counter 2 (at 8MHz) [reac Resolution | Moximum time setting | 000 1.05 5 . 001 1.02 ms 010 320s ont 1 Example : Sets the Timer mode with source clock fe/23 [Hz] and generates an interrupt every 25 ms (at fc = 8 MHz). Low {TREG2), GASH @ Sets the TREG2 (25 ms + 29/ fc = G1AB}) SET (EIRH).EF14 i Enables INTTC2 interrupt fa to (TC2CR), 001011008 j Starts TC2 (2) Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TREG2 are compared with the contents of the up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The maximum frequency applied to the TC2 pin is fe/24 [Hz] in NORMAL or IDLE mode. But, a pulse width of 2 machine cycles or more is required for both “H” and “U" level. Example : Sets the Event counter mode and generates an INTTC2 interrupt 640 counts later Low (TREG2), 640 } Setsthe TREGI set (EIRH).EF14 } Enables INTTC2 interrupt LD (TC2CR), 001111008 j Starts TC2 (3) Window mode In this mode, counting up is performed by an internal clock during “H” level of TC2 external pin input (Window pulse). The contents of TREG2 are compared with the contents of up-counter. Ifa match is found, an INTTC2 interrupt is generated, and the up-counter is cleared to "0". It is necessary that the maximum applied frequency must be considerably slower than the selected internal clock. Example : Inputs ”H" level pulse of 120 ms or more and generates interrupt. (at fe = 8 MHz). tow (TREG2), 007RH +: Sets TREG2 (120 ms + 213/fc = 0078),) SET (EIRH).EF14 3 Enables INTTC2 interrupt fa Lo (TC2cR), 001001018 j Starts TC2 87CA05A-54

TC? pininput Internal clock H H i l i t i counter ° KEK Xe XX HEX X2 REG? ee Match |] Counter clear INTTC2 interrupt Figure 2-21. Window mode timing chart B7C405A-55

2.9 Key Wake Up

The 87C405A can control STOP mode with four pins such as P62, P63, P64 and P65 other than P76 INTS/STOP). When the STOP mode is controlled in port inputs of P62, P63, P64 and P65, system register 1 (SYSCR1) must start the STOP mode (Level release mode). STOP mode control register storcr 26 5 4 3 2 1 0 oozry) [=] = [st0°s [store [stors[storae] = T=] nitiat value =-0000-") store P62 port releases from STOP mode o: Disable 1: Enable STOP3 P63 port releases from STOP mode ©: Disable 1: Enable , 0: Disable Read/Write stora P64 port releases from STOP mode 1: Enable sToPs P65 port releases from STOP mode 0: Disable 1: Enable Figure 2-22. Stop mode control register STOP mode control circuit STOP mode P70 (INTS/3TOP) control signal P62 (STOP?) P63 (STOPS) P64 (sTOPA) He] P65 (STOPS) ‘EEL stoPcr $1413 |2 Figure 2-23. Stop mode control circuit Each bit of P62 to P65 can be individually connected with internal pull-up resistor under the STOP mode control register (STOPCR). Data input ten, Date output Senpo“* P6i(i=2to5) Control input sToPi Figure 2-24, Port P6i (i=2to 5) Note: In case of using PO2 to P65 as key wake-up inpul, use P76 (including INTS/STOP) only as en input, donotsetit as output. 87CA05A-56

(1) Control pins The input/output circuits of the 87C405A control pins are shown below. a Oe. enable te High-frequency resonator XIN Input VDD vod i “s i Xour ouput Ro, connecting pin Ry =1.2M0 (typ) =15kQ (typ) XIN xOUT o (yp) wo Sink open drain output Cf R= Hysteresis input RESET vo | Address-trap-reset Pulr-up resistor Watchdog-timer-rese Rw=220kQ (typ) System-clock-reset Rika (yp) initiat "Hi-Z" yop STORANTS Input Disable miexe Hysteresis input (P76) va R Retka (typ) P76 STOPANTS <y — Initial “Hi-Z” Riv yoo Hysteresis input i= 25 STOP! Input (6i) Disable R Pull-up resistor si Riy=70kQ (typ.) Reika (yp) STOP: vod R Pull-down resister TEST Input Ryw=70kA (typ.) Rw R=1kO (typ) B/C405A-57 .

(2) Input /output ports The input/output circuits of the 87C405A input / output ports are shown below. Port | vO Input / Output Circuitry and Code [Remarks S| Initial “Hi-Z” DD Tri-state VO Te Hystereci input pr | vo isable . Ret ko (typ) Initial "Hi-2” VoD Iristate vO (ES R= 1k (typ) Disable + R Initial *Hi-2" yoo Tri-state VO P-ch Control R=ikN (typ)

7 Disable R

a 87C405A-58

Electrical Characteristics

Absolute maximum ratings (Vss=0¥) PARAMETER CONDITIONS RATINGS UNIT fnonvonge | aw | eee |v | : | sz [ma | ToL tour fiom | oom fruroe, eT | [= town fovee Tn Jou 2a won| to [P67 [| | Jstooeremernre [veo fates | Operating Temperate a ee Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Recommended operating conditions (Vss=0V, Topr= ~30t0 70°C) [_varaneren [ovunon| ows | conommons in| en [ uni | IDLE mode ‘fc [NORMAL mode Supply Voltage Voo [42 muz| [OLE mode. 27 v sropmode | 20 Vooe4.5V Vpp 0.75 input High Voltage Yoo v [we | | arvsinensy | een Von? 4.5V Input Low voltage v [vo | | arvsveneasy | [Vop=4.5to5.5v a | Clock Frequency fe | XIN, XOUT Vepn2T tos SV a | Notel: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage. operating temperature range, specified AC/DC values ete.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Notez: Clock frequency fc : Supply voltage range Is specified in NORMAL mode and IDLE mode. Note3: Minimum of clock frequency : 400 kHz 5 fegck B7CQ05A-59

D.C. characteristics (Vss = OV, Topr= -30to 70°C) [__parawerer rvwoouf ins CONDITIONS [ in. | typ. [ax [uns] [rysteresivoniage | Vas [Hyteredinguts tT | os] - tv | twa | RESET, ‘STOP! Vin=5.5V/0V [Ras_[ TEST es ee [tea [stor imate ia | 70 | 80 | [Seiptusett Curent | ty [Tistetepens [Vop=svivourasswv [= | - | 2 [oa] Vop=45V, ln=-07ma [ar] = | - | v | [ouwutiow voneys | vou [excepixour andr? |vopmaaviigeisma | - | - [ua |v | [outouttowcurrent [ox [p7 Vana V.Vztov | - | 7 | - | ma] ees [0 | supply Curretin [2 |= Fao [ee | NORMAL mode Vpoe55V [ae [=P 26 [ar | oe | PEE supply Current in DLE Wmessvion | Tig = [24 [39 | mode "Five [= | 19] 35 | Lis pas Pas | NORMAL mode Vesey fe (tee = pos [12 | coe hanna [ve [= [oa [0 | Gee oy | Leto fe | mode [Hee |= [os [09 | [we |= [03s [os | ‘Supply Current in Vop=5.5V. STOP mode Vin =5.3V/0.2V “ Note 2: Input Current IIN1, IIN3 : The current through resistor is not included, when the input resistor (pull-up or pull- down) is contained. 87C405A-60

A.C. characteristics (I) (Vsg=0V, Vpp=4.5to 5.5 V, Topr= - 30to 70°C) PARAMETER symeot] _cowomions in| yp. | woe | unr] In NORMAL mode Machine Cycle Time tey \\s In IDLE mode High Level Clock Pulse Width | twen_| For external clock operation A.C. characteristics (11) (ss =0V, Vpp=2.7 10 5.5V, Topr= ~30t070°C) In NORMAL mode Machine Cycle Time ty s Low Level Clock Pulse Width fe=4.2MHz 87C405A-61

Recommended oscillating conditions (1) (Vss = 0V. Vop = 4.5 to 5.5 V. Topr= -30to 70°C) iat (vOD = 4.58055 ¥) GRATA SAB.OOMTZ CSTB.OOMTW Ceramic Resonator STS8.OOMT. i (VDD =2.7t0 5.5V) are (VDD = 2.710 5.5 V) | KYOCERA KBR4.OMS [sor 8MHz DD = 4.510 5.5V) | TOYOCOM 2108 8.0000 Crystal Oscillator Mz TOYOCOM 2048 4.000 Recommended oscillating conditions (II) (Vsg=0V, Vpp = 2.7 t0 5.5 V, Topr= -30to 70°C) PARAMETER Oscillator | fea _| Recommended Oscillator 4.19MHz MURATA, CSA4.19MG 30pF [ sopr | (VDD = 2.; . High-frequency , MURATA CSAAOOMG |_—_—30pF | 30pF | . Ceramic Resonator csas.oomec [= = Oscillation 4MHz MURATA CST4.00MGW (VDD = 2.7 to 5.5 V) a CSTC4.00MG (1) High-frequency Oscillation Note: When used in high electric field such as a picture tube, the package is recommended to be electrically shielded to maintain a regularaperation ee 87C405A-62

SOP28-P-450-1.27 Unit: mm ze 13 | al = it 14 19.0MAX. 18,520.2 gg fe Fs IT 8 3 =f s s 1,020.2 TO wee

SDIP28-P-400-1.78 Unit: mm fasscansocnanl 3 > i i Oe oe ee eo ee OO a nn 3 3 ITT TT EO TE Es) | y . ~ so 3 87C405A-64