ICS879S216I-02 IDT | Alldatasheet
Document overview
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Technical content
Features
- High speed 2:2 differential divider
- Two differential LVPECL or LVDS output pairs
- Four selectable divide combinations
- PCLKx can accept the following input levels: LVPECL, LVDS, CML
- Maximum input frequency: 2.5GHz
- Propagation delay: 0.8ns (minimum), 1.6ns (maximum)
- Output Skew: 25ps (maximum)
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 5) package Table 1B. SEL_OUT Function Table Outputs Output Level Supply V CC_TAPQ[1:0], nQ[1:0] LVPECL 2.5V V CC LVPECL 3.3V V CC LVDS 2.5V V CC LVDS 3.3V Float Input Outputs SEL_OUT Q[1:0], nQ[1:0]
1 LVPECL (default)
4mm x 4mm x 0.95mm package body K Package Top View Pin AssignmentBlock Diagram
ICS879S216AKI-02 REVISION A APRIL 8, 2011 2 ©2011 Integrated Device Technology, Inc. Table 2. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 3. Pin Characteristics NOTE: CLK_SEL is an asynchronous control. 1 CLK_SEL Input Pulldown Clock select input. S ee Table 4B. LVCMOS/LVTTL interface levels. 2 PCLK0 Input Pulldown Non-inverting di fferential LVPECL clock input. Pulldown Inverting differential LVPECL clock input. 4 PCLK1 Input Pulldown Non-inverting di fferential LVPECL clock input. Pulldown Inverting differential LVPECL clock input. 6 SEL_OUT Input Pullup Select pin. See Tabl e 1B. LVCMOS/LVTTL interface levels. 7, 18 V CC Power Power supply pins. 8V CC_TAP Power Power supply pin. See Table 1A. 9, 13, 23 V EE Power Negative supply pins. 16, 17, 24 nc Unused No connect. F_SEL0 Input Pullup Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. 19, 20 nQ1, Q1 Output Different ial output pair. LVPECL or LVDS interface levels. 21, 22 nQ0, Q0 Output Different ial output pair. LVPECL or LVDS interface levels.
0 PCLK0, nPCLK0 (default)
1 PCLK1, nPCLK1
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 3 ©2011 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5B. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5C. LVDS Power Supply DC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C Table 5D. LVDS Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, IO (LVDS) Continuos Current Surge Current 50mA 100mA 10mA 15mA Package Thermal Impedance, θJA 49.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Power Supply Voltage 3.135 3.3 3.465 V VCC_TAP Power Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 65 mA Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 60 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 95 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Power Supply Voltage 2.375 2.5 2.625 V VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 90 mA
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 4 ©2011 Integrated Device Technology, Inc. Table 5E. LVCMOS/LVTTL DC Characteristics, VCC = VCC_TAP = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5F. LVPECL DC Characteristics, VCC = VCC_TAP = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 3: Outputs terminated with 50Ω to VCC – 2V. Table 5G. LVDS DC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C Table 5H. LVDS DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2.2 V CC + 0.3 V VCC = 2.625V 1.7 V CC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current CLK_SEL V CC = VIN = 3.465V or 2.625V 150 µA F_SEL[1:0], SEL_OUT VCC = VIN = 3.465V or 2.625V 10 µA IIL Input Low Current CLK_SEL V CC = 3.465V or 2.625V, VIN = 0V -10 µA F_SEL[1:0], SEL_OUT VCC = 3.465V or 2.625V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK0, nPCLK0, PCLK1, nPCLK1 VCC = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current PCLK0, PCLK1 V CC = 3.465V or 2.625V -10 µA nPCLK0, nPCLK1 VCC = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 V EE + 0.5 V CC – 0.85 V VOH Output High Voltage; NOTE 3 V CC – 1.4 V CC – 0.8 V VOL Output Low Voltage; NOTE 3 V CC – 2.0 V CC – 1.6 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage SEL_OUT = 0 247 454 mV ∆VOD VOD Magnitude Change SEL_OUT = 0 50 mV VOS Offset Voltage SEL_OUT = 0 1.125 1.375 V ∆VOS VOS Magnitude Change SEL_OUT = 0 50 mV Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage SEL_OUT = 0 247 454 mV ∆VOD VOD Magnitude Change SEL_OUT = 0 50 mV VOS Offset Voltage SEL_OUT = 0 1.1 1.375 V ∆VOS VOS Magnitude Change SEL_OUT = 0 50 mV
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 5 ©2011 Integrated Device Technology, Inc. Table 6A. LVPECL AC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined according with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section. Table 6B. LVPECL AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C For NOTES, see Table 6A above. Symbol Parameter Test Conditions Minimum Typical Maximum Units fIN Input Frequency 2.5 GHz fOUT Output Frequency F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 0.8 1.6 ns tsk(i) Input Skew 60 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps tR / tF Output Rise/Fall Time 20% to 80% 90 250 ps odc Output Duty Cycle 47 53 % MUXISOLATION MUX Isolation; NOTE 5 >100 dB Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fIN Input Frequency 2.5 GHz fOUT Output Frequency F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 0.8 1.6 ns tsk(i) Input Skew 60 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps tR / tF Output Rise/Fall Time 20% to 80% 90 250 ps odc Output Duty Cycle 47 53 % MUXISOLATION MUX Isolation >100 dB
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 6 ©2011 Integrated Device Technology, Inc. Table 6C. LVDS AC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined according with JEDEC Standard 65. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section.. Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C For NOTES, see Table 6C above. Symbol Parameter Test Conditions Minimum Typical Maximum Units fIN Input Frequency 2.5 GHz fOUT Output Frequency F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 0.8 1.6 ns tsk(i) Input Skew 75 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps tR / tF Output Rise/Fall Time 20% to 80% 70 250 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation >100 dB Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fIN Input Frequency 2.5 GHz fOUT Output Frequency F_SEL[1:0] = 00 1.25 GHz F_SEL[1:0] = 01 625 MHz F_SEL[1:0] = 10 312.5 MHz F_SEL[1:0] = 11 156.25 MHz tp LH Propagation Delay, Low-to-High; NOTE 1 0.8 1.6 ns tsk(i) Input Skew 75 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps tR / tF Output Rise/Fall Time 20% to 80% 70 250 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation >100 dB
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 7 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit Differential Input Level 2.5V LVPECL Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit Propagation Delay SCOPE Qx nQx LVPECL VEE VCC, -1.3V±0.165V VCC_TAP SCOPE Qx nQx LVDS 3.3V±5% POWER SUPPL Y +–Float GND VCC VCC_TAP = Float VCC nPCLK[0:1] PCLK[0:1] VEE V CMR Cross Points V PP SCOPE Qx nQx LVPECL VEE VCC, -0.5V±0.125V VCC_TAP SCOPE Qx nQx LVDS 2.5V±5% POWER SUPPL Y +–Float GND VCC, VCC_TAP tpLH nQ[0:1] Q[0:1] PCLK0, PCLK1 nPCLK0, nPCLK1
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 8 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued MUX Isolation Part-to-Part Skew LVDS Output Rise/Fall Time Input Skew Output Skew LVPECL Output Rise/Fall Time Amplitude (dB) Spectrum of Output Signal Q MUX_ISOL = A0 – A1 (fundamental) Frequencyƒ MUX selects static input MUX selects active input clock signal tsk(pp) Part 1 Part 2 nQx Qx nQy Qy 20% 80% 80% 20% tR tF VOD nQ[0:1] Q[0:1] tPD2 tPD1 tsk(i) = |tPD1 - tPD2| tsk(i) nPCLK1 PCLK1 nQ Q nPCLK0 PCLK0 tsk(o) nQx Qx nQy Qy 20% 80% 80% 20% tR tF VSWING nQ[0:1] Q[0:1]
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 9 ©2011 Integrated Device Technology, Inc. Parameter Measurement Information, continued Offset Voltage Setup Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup out out LVDSDC Input ➤ VOS/∆ VOS VDD tPW tPERIOD tPW tPERIOD odc = x 100% nQ[0:1] Q[0:1] 100 out out LVDSDC Input VOD/∆ VOD VDD
ICS879S216AKI-02 REVISION A APRIL 8, 2011 15 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale
ICS879S216AKI-02 REVISION A APRIL 8, 2011 16 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS879S2162I-02. Equations and example calculations are also provided. The total power dissipation for the ICS879S216I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 49.5°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
ICS879S216AKI-02 REVISION A APRIL 8, 2011 17 ©2011 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 8. Figure 8. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
ICS879S216AKI-02 REVISION A APRIL 8, 2011 18 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS879S2162I-02. Equations and example calculations are also provided. load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 49.5°C/W per Table 8 below. Table 8. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
ICS879S216AKI-02 REVISION A APRIL 8, 2011 19 ©2011 Integrated Device Technology, Inc. Table 9. θJA vs. Air Flow Table for a 24 Lead VFQFN
ICS879S216AKI-02 REVISION A APRIL 8, 2011 20 ©2011 Integrated Device Technology, Inc. Table 10. Package Dimensions package dimensions are in Table 10.
- Type A: Chamfer on the paddle (near pin 1)
- Type C: Mouse bite on the paddle (near pin 1)
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER ICS879S216AKI-02 REVISION A APRIL 8, 2011 21 ©2011 Integrated Device Technology, Inc.
Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.
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