87993AYILF

87993I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
• PDF pages: 18

Technical content

1-to-5 Differential-to-3.3V LVPECL PLL Clock Driver W/Dynamic Clock Switch 87993I DATASHEET 87993I REVISION C 2/18/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 87993I is a PLL clock driver designed specifi cally for re- dundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signal frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feed- back is used to also provide zero delay buffer performance. The 87993I Dynamic Clock Switch (DCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the DCS will switch to the good secondary clock and phase/ frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated.

FEATURES

• Five differential 3.3V LVPECL outputs
• Selectable differential clock inputs
• CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 50MHz to 250MHz
• VCO range: 200MHz to 500MHz
• External feedback for “zero delay” clock regeneration with confi gurable frequencies
• Cycle-to-cycle jitter (RMS): 20ps (maximum)
• Output skew: 70ps (maximum), within one bank
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
• Pin compatible with MPC993 32-Lead QFP (LQFP) 7mm x 7mm x 1.4mm package body Y Package Top View 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 V CC INP0BAD INP1BAD CLK_SELECTED V EE nEXT_FB EXT_FB V EE nQA1 QA1 nQA0 QA0 VCC VCCA MAN_OVERRIDE PLL_SEL VEE nCLK1 CLK1 CLK_SEL nCLK0 CLK0 nALARM_RESET nMR V CC nQB2 QB2 nQB1 QB1 nQB0 QB0 VCC 87993I PIN ASSIGNMENT BLOCK DIAGRAM PLL Dynamic Switch Logic nQB0 QB0 nQB1 QB1 nQB2 QB2 nQA0 QA0 nQA1 QA1 PLL_SEL CLK_SELECTED INP1BAD INP0BAD MAN_OVERRIDE ALARM_RESET SEL_CLK nCLK0 CLK0 nCLK1 CLK1 nEXT_FB EXT_FB nMR

2 REVISION C 2/18/15

TABLE 1. PIN DESCRIPTIONS enabled. LVCMOS / LVTTL interface levels. SEL_CLK. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels. 6 CLK1 Input Pulldown Non-inverting differential clock input. 7 nCLK1 Input Pullup Inverting differential clock input. EE Power Negative supply pins. 10 EXT_FB Input Pulldown Differential external feedback. 11 nEXT_FB Input Pullup Differential external feedback.

13 CLK_SELECTED Output LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1

is selected. LVCMOS / LVTTL interface levels.

14 INP1BAD Output

15 INP0BAD Output

18, 19 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 20, 21 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 22, 23 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 25, 26 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 27, 28 nQA0, QA0 Output Differential output pair. LVPECL interface levels. CCA Power Analog supply pin. 31 MAN_OVERRIDE Input Pulldown Manual override. When HIGH, disables internal clock switch circuitry. LVCMOS / LVTTL interface levels.

32 PLL_SEL Input Pullup

Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS

3 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 80 180 mA ICCA Analog Supply Current 15 20 mA TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS Inputs 2 3.3 V VIL Input Low Voltage LVCMOS Inputs -0.3 0.8 V IIH Input High Current SEL_CLK, MAN_ OVERRIDE VIN = VCC = 3.465V 5 µA nALARM_RESET, PLL_SEL, nMR VIN = VCC = 3.465V 120 µA IIL Input Low Current SEL_CLK, MAN_ OVERRIDE VIN = 0V, VCC = 3.465V -5 µA nALARM_RESET, PLL_SEL, nMR VIN = 0V, VCC = 3.465V -120 µA VOH Output High Voltage; NOTE 1 2.4 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information Section, “3.3V Output Load AC Test Circuit diagram”. Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK0, CLK1, EXT_ FB VIN = VCC = 3.465V 5 µA nCLK0, nCLK1, nEXT_FB VIN = VCC = 3.465V 120 µA IIL Input Low Current CLK0, CLK1, EXT_ FB VIN = 0V, VCC = 3.465V -5 µA nCLK0, nCLK1, nEXT_FB VIN = 0V, VCC = 3.465V -120 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 V EE + 0.5 V CC - 0.85 V NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

4 REVISION C 2/18/15

TABLE 4. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = -40°C TO 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: These parameters are guaranteed by characterization. Not tested in production. when the PLL is locked and the input reference frequency is stable. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Specifi cation holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 5: Specifi cation holds for a clock switch between two signals no greater than ±p out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 1: Outputs terminated with 50W to VCC - 2V.

5 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH 87993I DATA SHEET

6 REVISION C 2/18/15

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 87993I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA pin. FIGURE 1. POWER SUPPLY FILTERING 10Ω VCCA 10μF .01μF 3.3V .01μF VCC The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 2B. LVPECL OUTPUT TERMINATIONFIGURE 2A. LVPECL OUTPUT TERMINATION drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS POWER SUPPLY FILTERING TECHNIQUES

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH 87993I DATA SHEET

8 REVISION C 2/18/15

FIGURE 4C. CLK/nCLK I NPUT DRIVEN BY 3.3V LVPECL D RIVER FIGURE 4B. CLK/nCLK I NPUT DRIVEN BY 3.3V LVPECL D RIVER FIGURE 4D. CLK/nCLK I NPUT DRIVEN BY 3.3V LVDS D RIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are FIGURE 4A. CLK/nCLK I NPUT DRIVEN BY IDT’ S LVHSTL DRIVER examples only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 4A, the input termination applies for IDT’s LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH 87993I DATA SHEET

10 REVISION C 2/18/15

FIGURE 5B. PCB BOARD LAYOUT FOR 87993I The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the pow- er pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the trans- mission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic imped- ance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is un- avoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The series termination resistors should be located as close to the driver pins as possible.

This section provides information on power dissipation and junction temperature for the 87993I. Equations and example calculations are also provided. The total power dissipation for the 87993I is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180 = 624mW
• Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 30.2mW = 151mW Total Power_MAX (3.465V, with all outputs switching) = 624mW + 151mW = 775mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 5. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION

12 REVISION C 2/18/15

1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.

• For logic high, V OUT = VOH_MAX = VCC_MAX – 1.0V (VCC_MAX - VOH_MAX) = 1.0V
• For logic low, V OUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

14 REVISION C 2/18/15

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH 87993I DATA SHEET

16 REVISION C 2/18/15

Rev Table Page Description of Change Date A T4 4 AC Table - deleted Note 6. Added “Wiring the Differential Input to Accept Single Ended Levels”. 1/16/03 B 9 & 10 Features Section - changed VCO max. from 360MHz to 500MHz. Pin Descriptions Table - revised nMR description. Pin Characteristics Table - changed C IN from max. 4pF to typical 4pF. Absolute Maximum Ratings - changed VO to IO and included Continuous Current and Surge Current AC Characteristics Table - changed fVCO from 360MHz to 500MHz. t PD - added test conditions to CLKx to EXT_FB. Added another line with 500MHz test conditions. odc - added test conditions. Added Differential Clock Input Interface in the Application Information section. Added Schematic Example. 5/21/03 CT 8 1 5 Updated datasheet’s header/footer with IDT from ICS. Removed “ICS” prefi x from Part/Order Number column. Added Contact Page. 7/26/10 Updated data sheet format 2/18/15

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