879893AYILF

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Technical content

Features

• Twelve LVCMOS/LVTTL outputs (two banks of six outputs); One QFB feedback clock output
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types: LVCMOS, LVTTL
• Automatically detects clock failure
• IDCS on-chip intelligent dynamic clock switch
• Maximum output frequency: 200MHz
• Output skew: 50ps (maximum), within bank
• Cycle-to-cycle (FSEL3=0, VDD=3.3V±5%): 150ps (maximum)
• Smooth output phase transition during clock fail-over switch
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 87973i 1 2 3 4 5 6 7 8 9 10 11 12 GND QA0 QA1 VDD GND QA2 QA3 VDD GND QA4 QA5 VDD GND QB0 QB1 VDD GND QB2 QB3 VDD GND QB4 QB5 VDD GND QFB FB nMAN/A VDD CLK0 CLK1 VDDA nALARM0 nALARM1 CLK_IND GND nALARM_RST REF_SEL nPLL_EN GND FSEL0 FSEL1 GND FSEL2 FSEL3 nOE/MR VDD VDD 36 35 34 33 32 31 30 29 28 27 26 25 879893 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Pin AssignmentSimplified Block Diagram 879893 Datasheet Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator

2©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017

879893 Datasheet

QA0:QA5 QB0:QB5 QFB nALARM0 nALARM1 CLK_IND CLK0 CLK1 FB REF_SEL nMAN/A nALARM_RST nPLL_EN FSEL[0:3] nOE/MR Pulldown Pulldown Pulldown Pulldown Pullup Pullup Pulldown Pulldown Pulldown

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. GND Power Power supply ground. 2 QFB Output Clock feedback output. LV CMOS / LVTTL interface levels. 3 FB Input Pulldown Feedback control input. LVCMOS / LVTTL interface levels. requires nPLL_EN = 0. LVCMOS / LVTTL interface levels. 6, 7 CLK0, CLK1 Input Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. 8V DDA Power Analog supply pin. 9 nALARM0 Output When LOW, indicates clock failure on CLK0. LVCMOS / LVTTL interface levels. 10 nALARM1 Output When LOW, indicates clock failure on CLK1. LVCMOS / LVTTL interface levels.

11 CLK_IND Output

reference clock. When HIGH, CLK1 is the reference clock. LVCMOS / LVTTL interface levels. QB2, QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. internal dividers are reset and the outputs are in a high-impedance state. LVCMOS / LVTTL interface levels. FSEL1, FSEL0 Input Pulldown Clock frequency selection and configuration of clock divider modes. LVCMOS / LVTTL interface levels. reference clock signal fREF. LVCMOS / LVTTL interface levels.

34 REF_SEL Input Pulldown

source. LVCMOS / LVTTL interface levels. 35 nALARM_RST Input Pullup Resets the alarm flags and selected reference clock. LVCMOS / LVTTL interface levels. QA3, QA4, QA5 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.

Table 2. Pin Characteristics Table 3. Clock Frequency Function Table

5©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 195 mA IDDA Analog Supply Current 13 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 173 mA IDDA Analog Supply Current 13

6©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Unless otherwise noted, outputs terminated with 50 to VDD/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage FSEL[0:3], FB, nOE/MR, nMAN/A, nALARM_RST[0:1], nPLL_EN, REF_SEL VDD = 3.465V -0.3 0.8 V FSEL[0:3], FB, nOE/MR, nMAN/A, nALARM_RST, nPLL_EN, REF_SEL V DD = 2.625V -0.3 0.7 V CLK0, CLK1 V DD = 3.465V or 2.625V -0.3 1.3 V IIH Input High Current nMAN/A, nALARM_RST VDD = VIN = 3.465V or 2.625V 5 µA CLK0, CLK1, FB, nOE/MR, FSEL[0:3], nPLL_EN, REF_SEL V DD = VIN = 3.465V or 2.625V 200 µA IIL Input Low Current nMAN/A, nALARM_RST VDD = 3.465V or 2.625V, VIN = 0V -200 µA CLK0, CLK1, FB, nOE/MR, FSEL[0:3], nPLL_EN, REF_SEL VDD = 3.465V or 2.625V, VIN = 0V -5 µA VOH Output High Voltage VDD = 3.465V, IOH = -24mA 2.4 V VDD = 2.625V, IOH = -15mA 1.8 V VOL Output Low Voltage VDD = 3.465V, IOL = 24mA 0.55 V VDD = 3.465V, IOL = 12mA 0.30 V VDD = 2.625V, IOL = 15mA 0.6 V

7©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DD/2. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 7.5 200 MHz fREF Input Frequency 15 100 MHz BW PLL Closed Loop Bandwidth 0.8 to 4 MHz t(Ø) Propagation Delay, (Static Phase Offset, CLKx to FB); NOTE 1, 2, 3 VDD = 3.3V±5%; FSEL = 111x -35 120 ps VDD = 3.3V±5% -35 130 ps tsk(o) Output Skew; NOTE 1, 2, 3, 4 within bank 50 ps bank-to-bank 135 ps any output to QFB 315 ps t Rate of Period Change; NOTE 2 f REF = 62.5MHz, FSEL = 1000 160 ps/ cycle FSEL = XXX0 100 280 ps/ cycle FSEL = XXX1 200 425 ps/ cycle tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 3 FSEL3 = 0 150 ps FSEL3 = 1 190 ps tCYCLE Output Clock Period Deviation when switching from primary input to secondary; NOTE 2 fREF = 62.5MHz, FSEL = 1000 -600 700 ps -800 800 ps tjit(per) Period Jitter; NOTE 2, 3 FSEL3 = 0 150 ps FSEL3 = 1, measured on QBx 150 ps tjit(Ø) I/O Phase Jitter, (1 ); NOTE 2, 3 FB = 4; FSEL [0:2] = 100 or 111 (1) 25 ps FB = 6; FB = 8; FSEL [0:2] = 001, 011 or 110 (1) 35 ps FB = 16; FSEL [0:2] = 000 or 101 (1) 25 ps tR / tF Output Rise/Fall Time 20% to 80% 250 600 ps tPZL, tPZH Output Enable Time; NOTE 2 10 ns tPLZ, tPHZ Output Disable Time; NOTE 2 10 ns tL PLL Lock Time; NOTE 2 10 ms odc Output Duty Cycle 45 50 55 %

8©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fOUT Output Frequency 7.5 200 MHz fREF Input Frequency 15 100 MHz BW PLL Closed Loop Bandwidth 0.8 to 4 MHz t(Ø) Propagation Delay, (Static Phase Offset, CLKx to FB); NOTE 1, 2, 3 VDD = 3.3V±5%; FSEL = 111x -55 120 ps VDD = 3.3V±5% -55 130 ps tsk(o) Output Skew; NOTE 1, 2, 3, 4 within bank 50 ps bank-to-bank 135 ps any output to QFB 280 ps t Rate of Period Change; NOTE 2 f REF = 62.5MHz, FSEL = 1000 175 ps/ cycle FSEL = XXX0 260 ps/ cycle FSEL = XXX1 350 ps/ cycle tjit(cc) Cycle-to-Cycle Jitter; NOTE 2, 3 FSEL3 = 0 180 ps FSEL3 = 1 245 ps tCYCLE Output Clock Period Deviation when switching from primary input to secondary; NOTE 2 f REF = 62.5MHz, FSEL = 1000 -600 700 ps -800 850 ps tjit(per) Period Jitter; NOTE 2, 3 FSEL3 = 0 150 ps FSEL3 = 1, measured on QBx 150 ps tjit(Ø) I/O Phase Jitter, (1 ); NOTE 2, 3 FB = 4; FSEL [0:2] = 100 or 111 (1) 30 ps FB = 6; FB = 8; FSEL [0:2] = 001, 011 or 110 (1) 25 ps FB = 16; FSEL [0:2] = 000 or 101 (1) 30 ps tR / tF Output Rise/Fall Time 20% to 80% 250 600 ps tPZL, tPZH Output Enable Time; NOTE 2 10 ns tPLZ, tPHZ Output Disable Time; NOTE 2 10 ns tL PLL Lock Time; NOTE 2 10 ms odc Output Duty Cycle 45 50 55 %

9©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 Parameter Measurement Information 3.3V Output Load AC Test Circuit Output Skew Input/Output Phase Jitter 2.5V Output Load AC Test Circuit Cycle-to-Cycle Jitter Period Jitter SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDA t sk(o) VDD VDD Qx Qy ➤ ➤t(Ø) VOH VOL VOH VOL tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter t(Ø) mean = Static Phase Offset and I/O Phase Jitt er Where t(Ø) is any random sample, and t(Ø) mean is the averag e of the sampled cycles measured on the controlled edges VDD VDD CLK0, CLK1 FB SCOPE Qx GND 1.25V±5% -1.25V±5% VDD, VDDA ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA[0:5], QB[0:5] VOH VREF VOL Mean Period (First edge after trigger) Reference Point (Trigger Edge) 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram

10©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017 Parameter Measurement Information, continued Propagation Delay Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time CLK0, CLK1 FB tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA[0:5], QB[0:5] 20% 80% 80% 20% tR tF QA[0:5], QB[0:5]

11©2017 Integrated Device Technology, Inc. Revision B, January 10, 2017

Application Information

CLOCK REDUNDANCY AND REFERENCE SELECTION The 879893 accepts two LVCMOS/LVTTL single ended input clocks, CLK0 and CLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. The clock that is used by default as the reference is referred to as the primary clock, while the remaining clock is the redundant or secondary clock. Input signal REF_SEL determines which input is to be used as the primary and which is to be used as the secondary. When REF_SEL is driven HIGH, the primary clock input is CLK1, otherwise an internal pull down pulls this input LOW so that the primary clock input is CLK0. The output signal CLK_IND indicates which clock input is being used as the reference (LOW = CLK0, HIGH = CLK1), and will initially be at the same level as REF_SEL. FAILURE DETECTION AND ALARM SIGNALING Within the 879893 device, CLK0 and CLK are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period. Upon detection of a failure, the corresponding alarm signal, nALARM0 or nALARM1, is latched LOW. A HIGH-to-LOW transition on input signal nALARM_RST causes the alarm outputs to be reset HIGH, and the primary clock input is selected as the reference clock. Otherwise, an internal pull-up holds nALARM_RST HIGH, and the IDCS flags remain unchanged. If n_ALARM_RST is asserted when both of the alarm flag outputs are LOW, CLK0 is selected as the reference input. The device’s internal PLL is able to maintain phase/frequency alignment, and lock with the input as long as the input used as the reference clock does not fail. MANUAL CLOCK SWITCHING When input signal nMAN/A is driven LOW, the primary clock, as selected by REF_SEL, is always used as the reference, even when a clock failure is detected at the reference. In order switch between CLK0 and CLK1 as the primary clock, the level on REF_SEL must be driven to the appropriate level. When the level on REF_SEL is changed, the selection of the new primary clock will take place, and CLK_IND will be updated to indicate which clock is now supplying reference. This process serves as a manual safety mechanism to protect the stability of the PLL when a failure occurs on the reference. DYNAMIC CLOCK SWITCHING When input signal nMAN/A is not driven LOW, an internal pull-up pulls it HIGH so that Intelligent Dynamic Clock Switching (IDCS) is enabled. If IDCS is enabled, once a failure occurs on the primary clock, the 879893 device will automatically deselect the primary clock as the reference and multiplex in the secondary clock, but only if it is valid and has no failures. When a successful switch from primary to secondary has been accomplished, CLK_IND will be updated to indicate the new reference. This process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. OUTPUT TRANSITIONING After a successful manual or IDCS initiated clock switch, the 879893’s internal PLL will begin slewing to phase/frequency alignment, and will eventually achieve lock with the new input with minimal phase disturbance at the outputs. MASTER RESET OPERATION Applying logic HIGH to the nOE/MR input resets the internal dividers of the 879893 and disables the outputs QA0:QA5 and QB0:QB5 in high-impedance state. Logic LOW state at the nOE/MR input enables the outputs and internal dividers. RECOMMENDED POWER-UP SEQUENCE 1. Hold nOE/MR HIGH, drive nMAN/A LOW, and drive REF_SEL to the desired value during power up in order to reset internal dividers, disable the outputs in high-impedance state (nOE/MR = HIGH), select manual switching mode, and select the primary input clock. 2. Once powered up, assuming a stable clock free of failures is present at the primary input, the PLL will begin phase/frequency slewing as it attempts to achieve lock with the input reference clock. 3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0 and nALARM1 alarm flag outputs. 4. (Optional) Drive nMAN/A HIGH to enable IDCS mode. ALTERNATE POWER-UP SEQUENCE If both input clocks are valid before power up, the device may be powered up in IDCS mode. 1. During power up, select the desired primary clock input by REF_SEL and hold nOE/MR at logic HIGH level to reset the internal dividers and to disable the outputs QA0:QA5 and QB0:QB5 in high-impedance state. Logic high level at the nMAN/A input enables the IDCS mode. An internal bias resistor will pull the nMAN/A input to logic high level if nMAN/A is left open. 2. Once powered up, the PLL will begin phase/frequency slewing as it attempts to achieve lock with the input reference clock. 3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0 and nALARM1 alarm flag outputs.

resistor can be tied from the CLK input to ground. protection. A 1k resistor can be used. capacitor be connected to the VDDA pin. Figure 1. Power Supply Filtering

Figure 2. 879893 Schematic Example

Table 6. JA vs. Air Flow Table for a 48 Lead LQFP NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 48 Lead LQFP

DISCLAIMER Integrated Device Technology, In c. (IDT) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of IDT's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not conv ey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . Copyright ©2017 Integrated Device Tec hnology, Inc. All rights reserved. Tech Support www.idt.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters

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Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. Features Section - added lead-free bullet. Ordering Information Table - added lead-free Part/Order Number, Marking and Note. A 1 Product Discontinuation Notice - Last time buy expires November 2, 2016.