87974I

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Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator 87974I Data Sheet ©2016 Integrated Device Technology, Inc Revision E January 26, 20161 GENERAL DESCRIPTION The 87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynam- ically switching the PLL between two clock sources. Guaranteed low jitter and output skew characteristics make the 87974I ideal for those applications demanding well defi ned performance and repeatability.

FEATURES

• Fully integrated PLL
• Fifteen single ended 3.3V LVCMOS/LVTTL outputs
• Two LVCMOS/LVTTL clock inputs for redundant clock applica- tions
• CLK0 and CLK1 accepts the following input levels: LVCMOS/LVTTL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter: ±100ps (typical)
• Output skew: 350ps (maximum)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package PIN ASSIGNMENT 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View

©2016 Integrated Device Technology, Inc Revision E January 26, 20162 BLOCK DIAGRAM

©2016 Integrated Device Technology, Inc Revision E January 26, 20163 1÷4 PLL D D D D Q Q Q Q CLK_SEL CLK0 CLK1 FB_IN SEL_A PLL_SEL SEL_C FB_SEL(0:1) nMR/OE QA0:QA4 QB0:QB4 QC0:QC3 QFB SIMPLIFIED BLOCK DIAGRAM SEL_B FB_0 FB_1 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 SEL_C 0 ÷4 1 ÷6 SEL_B 0 ÷2 1 ÷4 SEL_A 0 ÷2 1 ÷4 VCO_SEL CLK_EN

TABLE 1. PIN DESCRIPTIONS GND Power Power supply ground. lowest frequency. The 87974I requires reset after any loss of PLL lock.

3 CLK_EN Input Pullup

are enabled. When LOW, clock outputs QAx:QCx are low. LVCMOS / LVTTL interface levels.

6 PLL_SEL Input Pullup

viders. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels. selects CLK0. LVCMOS / LVTTL interface levels. 9 CLK0 Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels. 10 CLK1 Input Pullup Reference clock input. LVCMOS / LVTTL interface levels. 11, 27, 42 nc Unused No connect. 13 V DDA Power Analog supply pin. Table 3E. LVCMOS / LVTTL interface levels. QA2, QA1, QA0 Output Bank A clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 17, 22, 26 V DDOA Power Output supply pins for Bank A clock outputs. 28 V DDOFB Power Output supply pin for QFB clock output. 29 QFB Output Clock output. LVCMOS / LVTTL interface levels.

31 FB_IN Input Pullup

“zero delay”. Connect to pin 29. LVCMOS / LVTTL interface levels. QB2, QB1, QB0 Output Bank B clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. DDOB Power Output supply pins for Bank B clock outputs. QC0 Output Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 45, 49 V DDOC Power Output supply pins for Bank C clock outputs. 52 VCO_SEL Input Pulldown Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

0 X HiZ HiZ HiZ HiZ

0 Bypass

1 PLL

0 CLK0

1 CLK1

TABLE 2. PIN CHARACTERISTICS NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB.

0 VCO/2

1 VCO/4

©2016 Integrated Device Technology, Inc Revision E January 26, 20166 TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 2.935 3.3 3.465 V VDDOx Output Supply Voltage; NOTE 1 3.135 3.3 3.465 V IDD Power Supply Current 121 mA IDDA Analog Supply Current 15 mA IDDOx Output Supply Current; NOTE 2 24 mA NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOFB. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOFB Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage SEL_A:SEL_C, nMR/OE, VCO_SEL, PLL_SEL, CLK_SEL, CLK_EN, FB_SEL0, FB_SEL1, FB_IN DD V CLK0, CLK1 2 V DD V VIL Input Low Voltage SEL_A:SEL_C, nMR/OE, VCO_SEL, PLL_SEL, CLK_SEL, CLK_EN, FB_SEL0, FB_SEL1, FB_IN 0.8 V CLK0, CLK1 0.8 V I IH Input High Current FB_SEL0, FB_SEL1, SEL_A:SEL_C, CLK0, VCO_ SEL, CLK_SEL V DD = VIN = 3.465V 100 µA CLK1, FB_IN, nMR/OE, PLL_ SEL, CLK_EN VDD = VIN = 3.465V 5 µA IIL Input Low Current FB_SEL0, FB_SEL1, SEL_A:SEL_C, CLK0, VCO_ SEL, CLK_SEL V IN = 0V, VDD = 3.465V -5 µA CLK1, FB_IN, nMR/OE, PLL_ SEL, CLK_EN VIN = 0V, VDD = 3.465V -100 µA VOH Output High Voltage; NOTE 1 2.4 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDOx/2. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = -40°C TO 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the VDD/2 point of the input to theVDDOx/2 of the output. when the PLL is locked and the input reference frequency is stable. NOTE 3: Defi ned as skew within a bank with equal load conditions. NOTE 4: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 6: Measured as peak-to-peak.

©2016 Integrated Device Technology, Inc Revision E January 26, 20168 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW OUTPUT RISE/FALL TIMECYCLE-TO-CYCLE JITTER OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD SYNC TO FEEDBACK PROPAGATION DELAY PARAMETER MEASUREMENT INFORMATION

©2016 Integrated Device Technology, Inc Revision E January 26, 20169 As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 87974I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, and V DDOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V DDA pin. The 10Ω resistor can also be replaced by a ferrite bead. POWER SUPPLY FILTERING TECHNIQUES FIGURE 1. POWER SUPPLY FILTERING

APPLICATION INFORMATION

INPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. LVCMOS C ONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left fl oating. We recommend that there is no trace attached.

©2016 Integrated Device Technology, Inc Revision E January 26, 201610 FIGURE 2A. 87974I LVCMOS/LVTTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE LAYOUT GUIDELINE The schematic of the 87974I layout example used in this layout guideline is shown in Figure 2A. The 87974I recommended PCB board layout for this example is shown in Figure 2B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. 3.3V LVCMOS Driver Zo = 50 OhmRS C13 0.01u 3.3V VDDO C12 0.1uF 0.1uF C10 0.1uF nMR Reset pulse or pull up VDD CLK_EN PLL_SEL SELA SELB SELC CLK_SEL RU6 SP RD6 RU5 SP RD2 SP RD4 RU4 SP RD5 RU7 SP RD3 SP RU3 RD7 RU2 0.1uF 0.1uF 0.1uF C16 10u 0.1uF 0.1uF C11 0.01u SP = Space (i.e. not intstalled) 0.1uF VDD 87974 GND1 nMR2 CLK_EN3 SELB4 SELC5 PLL_SEL6 SELA7 CLK_SEL8 CLK09 CLK110 nc11 VDD12 VDDA13 FB_SEL014 GND15 QA416 VDDOA17 QA318 GND19 FB_SEL120 QA221 VDDOA22 QA123 GND24 QA025 VDDOA26 GND 39 QB1 38 VDDOB 37 QB2 36 GND 35 QB3 34 VDDOB 33 QB4 32 FB_IN 31 GND 30 QFB 29 VDDOFB 28 nc 27 VCO_SEL 52 GND 51 QC0 50 VDDOC 49 QC1 48 GND 47 QC2 46 VDDOC 45 QC3 44 GND 43 nc 42 VDDOB 41 QB0 40 VDDO Zo = 50 Receiver Receiver Receiver Receiver Zo = 50 Zo = 50 Zo = 50 CLK_SEL CLK_EN SELB SELC VDD PLL_SEL SELA VCO_SEL Example of Reconfigurable Logic Control Input

©2016 Integrated Device Technology, Inc Revision E January 26, 201611 FIGURE 2B. PCB BOARD LAYOUT FOR 87974I The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the pow- er pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The series termination resistors should be located as close to the driver pins as possible.

TABLE 6. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision E January 26, 201615 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 10 & 11 Added Layout Guideline and PCB Board Layout. 4/2/02 A 3 Added simplifi ed block diagram. 4/4/02 A T7 12 Revised Package Outline drawing. Corrected Package Dimensions table to corre- spond with the Package Outline drawing. Update format throughout datasheet. 11/15/02 B T4A Pin Description table - updated nMR/OE and VDDOx pin descriptions. Changed IDD max. limit from 105mA max. to 118mA max., and IDDOx from 20mA max. to 22mA max. 3/20/03 B T3E Pin Characteristics Table - changed CIN 8pF max. to 4pF typical. FB Select Function Table - switched FB_SELx headings, FB_SEL1 heading is in column 1, FB_SEL0 heading is in column 2. 5/15/03 B T2 5 Pin Characteristics Table - added ROUT, Output Impedance row. Revised Package Outline. 7/9/03 C T4A 6 Change from die rev. A to B on part marking throughout data sheet. Change max. temperature to 70°C down from 85°C throughout data sheet. Power Supply DC Characteristics table - adjusted: V DDA from 3.135V min. to 2.9375V min., IDD from 118mA max. to 125mA max., and IDDOX from 22mA max. to 25mA max. 7/23/03 D T4A 6 Through out the data sheet the maximum temperature was changed from 70°C to 85°C. Power Supply DC Characteristics Table - IDD changed from 125mA max. to 121mA max. and IDDOx changed from 25mA max. to 24mA max. 8/4/03 D 2 & 3 Swaped labels for FB_SEL0 and FB_SEL1 in the Block Diagram and Simplifi ed Block Diagram. 2/9/04 D T3E 5 Corrected FB Select Function Table. 6/9/04 D T8 Added Recommendations for Unused Input and Output Pins. Ordering Information Table - part number and order number is now a revision C. Corrected lead-free part number and marking, and added lead-free note. 1/19/06 ET 8 1 4 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/26/10 E T1 4 Updated description of nMR/OE pin 04/18/13 E T8 Removed ICS from part numbers where needed. Features section - removed reference to leaded packages. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1/26/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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