87973DYI-147LFT

ICS87973I-147 IDT | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync
• Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs
• CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 10MHz to 150MHz
• VCO range: 240MHz to 500MHz
• Output skew: 200ps (maximum)
• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Compatible with PowerPC™ and Pentium™ Microprocessors
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS 1 2 3 4 5 6 7 8 9 10 11 12 13 3233343536373839 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL FSEL_FB1 QSYNC GNDO QC0 VDDO INV_CLK QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO GNDI VDDA nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 FSEL_FB0 EXT_FB GNDO QFB VDD Pin Assignment ICS87973I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 2 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Block Diagram SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC CLK nCLK VCO_SEL PLL_SEL REF_SEL EXT_FB CLK0 CLK1 Pullup Pullup Pullup Pullup Pullup Pullup CLK_SEL Pullup Pullup FRZ_CLK Pullup Pullup Pullup Pullup Pullup Pullup FRZ_DATAPullup INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] FSEL_FB2 nMR/OE Pullup

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 3 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Simplified Block Diagram SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ OUTPUT DISABLE CIRCUITRY PLL VCO RANGE 240MHz - 500MHz SYNC FRZ INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] nMR/OE 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 FSEL_ A1 A0 QAx 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷10 FSEL_ B1 B0 QBx 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FSEL_ FB2 FB1 FB0 QFB 0 0 ÷2 0 1 ÷4 1 0 ÷6 1 1 ÷8 FSEL_ C1 C0 QCx CLK nCLK VCO_SEL PLL_SEL REF_SEL EXT_FB CLK0 CLK1 Pullup Pullup Pullup Pullup Pullup Pullup CLK_SEL Pullup Pullup QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC FRZ_CLK Pullup FRZ_DATAPullup Pullup

Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1 GNDI Power Power supply ground. Master reset and output enable. When HIGH, enables the outputs. circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circ uitry. LVCMOS / LVTTL interface levels. 4 FRZ_DATA Input Pullup Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.

6 PLL_SEL Input Pullup

Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. or CLK1. When HIGH, CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 9, 10 CLK0, CLK1 Input Pullup Single-ended referenc e clock inputs. LVCMOS/LVTTL interface levels. 11 CLK Input Pullup Non-inverting differential clock input. DD/2 default when left floating. 13 V DDA Power Analog supply pin. 14 INV_CLK Input Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. GNDO Power Power supply ground. QC1, QC0 Output Single-ended Bank C clock output s. LVCMOS/ LVTTL interface levels. 37, 45, 49 VDDO Power Output power supply pins. FSEL_C0 Input Pullup Select pins for Bank C outputs. LV CMOS / LVTTL interface levels. See Table 3A. 25 QYSNC Output Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. 28 V DD Power Power supply pin. 29 QFB Output Single-ended feedback clock out put. LVCMOS / LVTTL interface levels. 31 EXT_FB Input Pullup External feedback. LVCMOS / LVTTL interface levels. QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels. FSEL_B0 Input Pullup Select pins for Bank B outputs. LV CMOS / LVTTL interface levels. See Table 3A. FSEL_A0 Input Pullup Select pins for Bank A outputs. LV CMOS / LVTTL interface levels. See Table 3A. QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels. 52 VCO_SEL Input Pullup Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.

Table 2. Pin Characteristics

Figure 1. Timing Diagrams

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 7 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. NOTE 2: VIL should not be less than -0.3V. NOTE 3: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 225 mA IDDA Analog Supply Current 20 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIN Input Current ±120 µA VOH Output High Voltage; NOTE 1 I OH = -20mA 2.4 V VOL Output Low Voltage; NOTE 1 I OL = 20mA 0.5 V VPP Peak-to-Peak Input Voltage; NOTE 2, 3 CLK, nCLK 0.3 1 V VCMRP Common Mode Input Voltage; NOTE 2, 3 CLK, nCLK V DD - 2 V DD - 0.6 V

Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C thermal equilibrium has been reached under these conditions. and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production.

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 9 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Parameter Measurement Information LVCMOS Output Load AC Test Circuit Cycle-to-Cycle Jitter LVCMOS Static Phase Offset Differential Input Level Output Skew Differential Static Phase Offset SCOPE Qx LVCMOS GND VDD, 1.65V±5% -1.65V±5% VDDO VDDA, ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB ➤ ➤ t(Ø) VDD VDD t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges CLK0, CLK1 EXT_FB V CMR Cross Points V PP VDD GND nCLK CLK tsk(o) Qx Qy t(Ø)➤ ➤ VDD VDD t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges nCLK EXT_FB nCLK

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 10 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Parameter Measurement Information, continued Output Duty Cycle/Pulse Width Period Output Rise/Fall Time

Application Information

Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. CLK Inputs For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB 0.8V 2V 2V 0.8V tR tF QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 14 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Schmatic Example Figure 6 shows a schematic example of using ICS87973I-147. This example shows general design of input, output termination, logic control input pull up/down and power supply filtering. In this example, the clock input is driven by an LVCMOS driver. ICS87973I-147 Schematic Layout 0.1uF R3 43 0.1uF RS Zo = 50 C11 0.01u RD1 Not Install C16 10u (U1-45) VDD 0.1uF RU2 Not Install VDD 0.1uF (U1-28) VDD=3.3VC6 0.1uF VDD (U1-37) R2 43 Serial Clcok To Logic Input pins Zo = 50 Set Logic Input to '0' R1 43 To Logic Input pins VDD R10 1K 0.1uF R9 1K Zo = 50 Set Logic Input to '1' ICS87973I-147 GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK VDDA INV_CLK GNDO QC3 VDDO QC2 FSEL_C1 FSEL_C0 QC1 VDDO QC0 GNDO QSYNC FSEL_FB1 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD FSEL_FB0 VCO_SEL GNDO QA0 VDDO QA1 GNDO QA2 VDDO QA3 FSEL_A0 FSEL_A1 FSEL_B0 FSEL_B1 VDD VDD Logic Input Pin Examples RD2 10 - 15 (U1-17) RU1 Serial Data Zo = 50 0.1uF LVCMOS CLOCK VDD

Table 7. θJA vs. Air Flow Table for a 52 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 8. Package Dimensions for 52 Lead LQFP

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 17 ICS87973DYI-147 REV. A DECEMBER 9, 2008

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 18 ICS87973DYI-147 REV. A DECEMBER 9, 2008 Revision History Sheet Rev Table Page Description of Change Date A T4B Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Added Recommendations for Unused Input and Output Pins section. Updated Differetnial Clock Input Interface section. UpdatePackage Outline and Package Dimensions Table. Ordering Information Table - added lead-free part number and marking. 12/9/08

LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER www.IDT.com © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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