87973 IDT | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 17

Technical content

Low Skew, 1-to-12 LVCMOS / LVTTL Clock Multiplier/Zero Delay Buffer 87973 Data Sheet ©2015 Integrated Device Technology, Inc December 7, 20151 P IN ASSIGNMENT GENERAL DESCRIPTION The 87973 is a LVCMOS/LVTTL clock generator. The 87973 has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The 87973 is a highly fl exible device. The three selectable in- puts (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. The input frequency range is 5MHz to 120MHz. The 87973 also has a QSYNC output which can by used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory mod- ule with zero delay.

FEATURES

  • Fully integrated PLL
  • Fourteen LVCMOS/LVTTL outputs; twelve clock outputs, one feedback, one sync
  • Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
  • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Output frequency range: 8.33MHz to 125MHz
  • VCO range: 200MHz to 480MHz
  • Output skew: 550ps (maximum)
  • Cycle-to-cycle jitter: ±100ps (typical)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free RoHS compliant package
  • Compatible with PowerPC™ and Pentium™ Microprocessors

87973 Data Sheet

©2015 Integrated Device Technology, Inc December 7, 20152 SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ VCO_SEL PLL_SEL REF_SEL CLK nCLK CLK0 CLK1 CLK_SEL EXT_FB FSEL_FB2 nMR/OE FSEL_A0:1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 FRZ_CLK FRZ_DATA INV_CLK QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC OUTPUT DISABLE CIRCUITRY DATA GENERATOR SYNC PULSE ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 POWER-ON RESET PHASE DETECTOR VCO LPF SYNC FRZ D Q D Q D Q D Q D Q D Q BLOCK DIAGRAM ÷4, ÷6, ÷8, ÷10

©2015 Integrated Device Technology, Inc December 7, 20153 SIMPLIFIED BLOCK DIAGRAM SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ OUTPUT DISABLE CIRCUITRY PLL VCO RANGE 200MHz - 480MHz SYNC FRZ INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] nMR/OE 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 FSEL_ A1 A0 QAx 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷10 FSEL_ B1 B0 QBx 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FSEL_ FB2 FB1 FB0 QFB 0 0 ÷2 0 1 ÷4 1 0 ÷6 1 1 ÷8 FSEL_ C1 C0 QCx QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC CLK nCLK CLK0 CLK1 CLK_SEL REF_SEL EXT_FB VCO_SEL PLL_SEL FRZ_CLK FRZ_DATA

TABLE 1. PIN DESCRIPTIONS 1 GNDI Power Power supply ground. LOW, resets the outputs to tristate and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. 4 FRZ_DATA Input Pullup Confi guration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.

6 PLL_SEL Input Pullup

MOS / LVTTL interface levels.

7 REF_SEL Input Pullup

Selects between CLK0 or CLK1 and CLK, nCLK inputs. When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1. LVCMOS / LVTTL interface levels.

8 CLK_SEL Input Pullup

9, 10 CLK0,CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 11 CLK Input Pullup Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 default when left fl oating. 13 V DDA Power Analog supply pin. 14 INV_CLK Input Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. 39, 47, 51 GNDO Power Power supply ground. QC1, QC0 Output Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 37, 45, 49 VDDO Power Output supply pins. FSEL_C0 Input Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. Diagrams. LVCMOS / LVTTL interface levels. 28 V DD Power Core supply pins. 29 QFB Output Feedback clock output. LVCMOS / LVTTL interface levels. 31 EXT_FB Input Pullup Extended feedback. LVCMOS / LVTTL interface levels. QB1, QB0 Output Bank B clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. FSEL_B0 Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. FSEL_A0 Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. QA1, QA0 Output Bank A clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. 52 VCO_SEL Input Pullup Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels. Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

FIGURE 1. TIMING DIAGRAMS

NOTE: Special thermal handling may be required in some confi gurations. NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V. conditions for extended periods may affect product reliability. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C when the PLL is locked and the input reference frequency is stable. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2015 Integrated Device Technology, Inc December 7, 20159 PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL CYCLE-TO-CYCLE JITTEROUTPUT SKEW STATIC PHASE OFFSET (LVCMOS) OUTPUT RISE/FALL TIME tPW & tPeriod STATIC PHASE OFFSET (DIFFERENTIAL)

©2015 Integrated Device Technology, Inc December 7, 201510

APPLICATION INFORMATION

USING THE OUTPUT FREEZE CIRCUITRY OVERVIEW To enable low power states within a system, each output of 87973 (Except QC0 and QFB) can be individually frozen (stopped in the logic “0” state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to elim- inate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the 87973 serial interface are FPGA’s and ASICs. PROTOCOL The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic “0” start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the 87973 can sample each FRZ_DATA bit with the rising edge of the FRZ_CLK signal. To place an output in the freeze state, a logic “0” must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic “1” must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic “0”, it is used for the start bit of the next cycle; otherwise, the device will wait and won’t start the next cycle until it sees a logic “0” bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state.

power supply isolation is required. FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

©2015 Integrated Device Technology, Inc December 7, 201512 FIGURE 5C. CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 5B. CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 5D. CLK/ NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 50R3 Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must mee t the VPP and VCMR input requirements. Figures 5A to 5D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are FIGURE 5A. CLK/ NCLK INPUT DRIVEN BY LVHSTL D RIVER examples only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 5A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V INPUTS: CLK INPUT: For applications not requiring the use of a clock input, it can be left fl oating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left fl oating. Though not required, but for additional protection, a 1k Ω resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left fl oating. There should be no trace attached.

TABLE 7. θJAVS. AIR FLOW TABLE NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. PACKAGE DIMENSIONS

TABLE 9. ORDERING INFORMATION

©2015 Integrated Device Technology, Inc December 7, 201516 REVISION HISTORY SHEET Rev Table Page Description of Change Date A T1 4 Pin Description Table - added pins 20 and 21. 9/9/02 A 2 Block Diagram - added missing dividers to the Data Generator. 10/18/02 B T4B 7 DC Characteristics table - updated VCMR values from GND + 1.5V min., VDD max. to VDD - 2V min., VDD - 0.6V max. 10/23/02 B Pin Description Table - corrected CLK Type to read Pullup from Pulldown. Revised Package Drawing. Corrected Package Dimensions table to correspond with the Package Drawing. 11/18/02 B 1 Added LVTTL to title. Corrected Package Outline to correspond with the Package Dimensions table. 12/10/02 C T4A Pin Characteristics - changed the CPD limit from 25pF typical to 18pf max. Power Supply Table - changed the IDD limit from 215mA max. to 225mA max. Application Information: Added sections, “Power Supply Filtering Techniques” and “Wiring the Differential Level...” Added “Differential Clock Input Interface” section. 3/21/03 C T2 5 Pin Characteristics - changed CIN from 4pF max. to 4pF typical. Corrected Freeze Data labeling on Figure 2A. 5/7/03 D T4A 7 Power Supply Table - changed V DDA minimum from 3.135V to 2.935V. 6/27/03 D T1 Pin Characteristics Table - added Pullup/Pulldown to pin 12, nCLK. Pin Characteristics Table - added to ROUT 5Ω min. and 12Ω max. 7/9/03 DT 9 Features section - added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking and note. 5/19/06 DT 9 1 5 Updated datasheet’s header/footer with IDT from ICS. Removed ICS”prefi x from Part/Order Number column. Added Contact Page. 8/15/10 D suffi x note. Updated DS header and footer. 12/7/15

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2015 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support