87972DYILF

87972I RENESAS | Alldatasheet

Document overview

• Manufacturer or author: rdvorak
• PDF pages: 18

Technical content

Low Skew, 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer 87972I Data Sheet ©2016 Integrated Device Technology, Inc Revision E January 25, 20161 P IN ASSIGNMENT GENERAL DESCRIPTION The 87972I is a low skew, LVCMOS/LVTTL Clock Generator. The 87972I has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The 87972I is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the 87972I can be used as a zero delay buffer/multiplier/divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. Input frequency range is 5MHz to 120MHz. The 87972I also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: 1. System Clock generator: Use a 16.66MHz Crystal to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply 19.44MHz from a back plane to 77.76MHz for the line Card ASICs and Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller ref- erence clock to the memory chips on a memory module with zero delay.

FEATURES

• Fully integrated PLL
• Fourteen LVCMOS/LVTTL outputs; (12) clocks, (1) feedback, (1) sync
• Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs
• CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 480MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS-compliant package
• Compatible with PowerPC™ and Pentium™ Microprocessors 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View

©2016 Integrated Device Technology, Inc Revision E January 25, 20162 SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ XTAL1 XTAL2 VCO_SEL PLL_SEL REF_SEL CLK0 CLK1 CLK_SEL EXT_FB FSEL_FB2 nMR/OE FSEL_A0:1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 FRZ_CLK FRZ_DATA INV_CLK QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC OUTPUT DISABLE CIRCUITRY DATA GENERATOR SYNC PULSE ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 POWER-ON RESET PHASE DETECTOR VCO LPF D Q D Q D Q D Q D Q D Q BLOCK DIAGRAM ÷4, ÷6, ÷8, ÷10

©2016 Integrated Device Technology, Inc Revision E January 25, 20163 QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC XTAL1 XTAL2 CLK0 CLK1 CLK_SEL REF_SEL EXT_FB VCO_SEL PLL_SEL SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ OUTPUT DISABLE CIRCUITRY PLL VCO RANGE 200MHz - 480MHz SYNC FRZ INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 FSEL_ A1 A0 QAx 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷10 FSEL_ B1 B0 QBx 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FSEL_ FB2 FB1 FB0 QFB 0 0 ÷2 0 1 ÷4 1 0 ÷6 1 1 ÷8 FSEL_ C1 C0 QCx nMR/OE SIMPLIFIED BLOCK DIAGRAM FRZ_CLK FRZ_DATA

TABLE 1. PIN DESCRIPTIONS 1 GNDI Power Power supply ground. (Hi-Z). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. 4 FRZ_DATA Input Pullup Confi guration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.

6 PLL_SEL Input Pullup

reference clocks. LVCMOS / LVTTL interface levels.

7 REF_SEL Input Pullup

CLK0 or CLK1. When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 9, 10 CLK0, CLK1 Input Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. 11, 12 XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. DDA Power Analog supply pin. 14 INV_CLK Input Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. 35, 39, 47, 51 GNDO Power Power supply ground. QC1, QC0 Output Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 37, 45, 49 VDDO Power Output supply pins. FSEL_C0 Input Pullup Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. Timing Diagrams. LVCMOS / LVTTL interface levels. 28 V DD Power Core supply pins. 29 QFB Output Feedback clock output. LVCMOS / LVTTL interface levels. 31 EXT_FB Input Pullup External feedback. LVCMOS / LVTTL interface levels. QB1, QB0 Output Bank B clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. FSEL_B0 Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. FSEL_A0 Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. QA1, QA0 Output Bank A clock outputs.7Ω typical output impedance. LVCMOS / LVTTL interface levels. VCO ÷ 2. LVCMOS / LVTTL interface levels. Pullup refers to internal input resistors. See table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

FIGURE 1. TIMING DIAGRAMS

NOTE: Special thermal handling may be required in some confi gurations. conditions for extended periods may affect product reliability. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 6. CRYSTAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 7. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C when the PLL is locked and the input reference frequency is stable. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision E January 25, 20169 PARAMETER MEASUREMENT INFORMATION CYCLE-TO-CYCLE JITTER3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW STATIC PHASE OFFSET OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

FIGURE 3. POWER SUPPLY FILTERING tied from XTAL_IN to ground. 1kΩ resistor can be tied from the CLK input to ground. protection. A 1kΩ resistor can be used. that there is no trace attached.

TABLE 8. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9. PACKAGE DIMENSIONS

TABLE 10. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision E January 25, 201616 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 1 4 Pin Description Table - added pins 20 and 21. 9/9/02 A 2 Block Diagram - added missing dividers to the Data Generator. 10/18/02 A 12 Revised Package Outline diagram. 12/5/02 B T4A Pin Characteristics - changed the C PD limit from 25pF typical to 18pf max. Power Supply Table - changed the IDD limit from 215mA max. to 250mA max. Application Information: Added section, “Power Supply Filtering Techniques”. 3/24/03 B T2 5 Pin Characteristics - changed CIN from 4pF max. to 4pF typical. Corrected Freeze Data labeling on Figure 2A. 5/8/03 C T4A Power Supply Table - changed minimum VDDA from 3.135V to 2.935V. Crystal Table - changed ESR from 80Ω to 50Ω. 6/27/03 C 11 Added Schematic Layout. 12/28/04 D T10 Features Section - add lead-free bullet. Pin Characteristics table - added 5Ω min. and 12Ω max to R OUT. Crystal Characteristics table - added Drive Level. Added Recommendations for Unused Input and Output Pins. Ordering Information table - added lead-free part number, marking and note. 11/29/05 D T10 15 Updated datasheet’s header/footer with IDT from ICS. Removed “”ICS”” prefi x from Part/Order Number column. Added Contact Page. 6/25/10 E T10 Removed ICS from part numbers where needed. Features section - removed reference to leaded package. Ordering Information - removed quantity from tape and reel. Deleted note below the table. Revision History - Corrected from Rev C to Rev D for 6/25/10. Updated header and footer. 1/25/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.