ICS87972I IDT | Alldatasheet

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87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PIN A SSIGNMENT GENERAL DESCRIPTION The ICS87972I is a low skew, LVCMOS/LVTTL Clock Generator. The ICS87972I has three selectable inputs and provides fourteen LVCMOS/LVTTL outputs. The ICS87972I is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the ICS87972I can be used as a zero delay buffer/multiplier/divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to- input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 8.33MHz to125MHz. Input frequency range is 5MHz to 120MHz. The ICS87972I also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. Example Applications: System Clock generator: Use a 16.66MHz Crystal to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. 2. Line Card Multiplier: Multiply 19.44MHz from a back plane to 77.76MHz for the line Card ASICs and Serdes. 3. Zero Delay buffer for Synchronous memory: Fan out up to twelve 100MHz copies from a memory controller ref- erence clock to the memory chips on a memory module with zero delay.

FEATURES

  • Fully integrated PLL
  • Fourteen LVCMOS/LVTTL outputs; (12) clocks, (1) feedback, (1) sync
  • Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs
  • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Output frequency range: 8.33MHz to 125MHz
  • VCO range: 200MHz to 480MHz
  • Output skew: 550ps (maximum)
  • Cycle-to-cycle jitter: ±100ps (typical)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Available in both standard andd lead-free RoHS-compliant packages
  • Compatible with PowerPC™ and Pentium™ Microprocessors FSEL_FB0 VDD QFB GNDO EXT_FB QB3 VDDO QB2 GNDO QB1 VDDO QB0 GNDO 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 V DDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL FSEL_FB1 QSYNC GNDO QC0 V DDO QC1 FSEL_C0 FSEL_C1 QC2 V DDO QC3 GNDO INV_CLK VDDA XT AL2 XT AL1 CLK1 CLK0 CLK_SEL REF_SEL PLL_SEL FSEL_FB2 FRZ_DATA FRZ_CLK nMR/OE GNDI 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View ICS87972I

87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ XT AL1 XT AL2 VCO_SEL PLL_SEL REF_SEL CLK0 CLK1 CLK_SEL EXT_FB FSEL_FB2 nMR/OE FSEL_A0:1 FSEL_B0:1 FSEL_C0:1 FSEL_FB0:2 FRZ_CLK FRZ_DATA INV_CLK QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC OUTPUT DISABLE CIRCUITRY DATA GENERATOR SYNC PULSE ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 POWER-ON RESET PHASE DETECTOR VCO LPF DQ DQ DQ DQ DQ DQ BLOCK D IAGRAM ÷4, ÷6, ÷8, ÷10

87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC XTAL1 XTAL2 CLK0 CLK1 CLK_SEL REF_SEL EXT_FB VCO_SEL PLL_SEL SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ OUTPUT DISABLE CIRCUITRY PLL VCO RANGE 200MHz - 480MHz SYNC FRZ INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 FSEL_ A1 A0 QAx 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷10 FSEL_ B1 B0 QBx 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FSEL_ FB2 FB1 FB0 QFB 0 0 ÷2 0 1 ÷4 1 0 ÷6 1 1 ÷8 FSEL_ C1 C0 QCx nMR/OE SIMPLIFIED B LOCK D IAGRAM FRZ_CLK FRZ_DATA

TABLE 1. PIN DESCRIPTIONS

TABLE 2. P IN CHARACTERISTICS

FIGURE 1. TIMING DIAGRAMS

conditions for extended periods may affect product reliability. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

TABLE 6. CRYSTAL CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 7. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION CYCLE-TO-CYCLE J ITTER3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS 1.65V±5% -1.65V±5% OUTPUT SKEW STATIC PHASE OFFSET OUTPUT RISE/FALL TIME t sk(o) VDDO VDDO 2Qy Qx OUTPUT D UTY C YCLE/PULSE WIDTH/PERIOD tPW tPERIOD VDDO VDDO VDDO tPW tPERIOD odc = QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB QA0:QA3, QB0:QB3, QC0:QC3, QSYNC, QFB ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

0.5V 2.4V 2.4V 0.5V tR tF ➤ ➤ t(Ø) VDD VDD CLK0, CLK1 EXT_FB (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset VDD, VDDA, VDDO GND

87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87972I provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10 Ω resistor along with a 10 μF and a .01 μF bypass capacitor should be connected to each V DDA pin. FIGURE 3. POWER SUPPLY FILTERING 10 Ω VDDA 10μF .01μF 3.3V .01μF VDD INPUTS: CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from the CLK input to ground. LVCMOS C ONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.

TABLE 8. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9. P ACKAGE DIMENSIONS

TABLE 10. O RDERING INFORMATION the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

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87972DYI www.idt.com REV. E JUNE 25, 2010 ICS87972I LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com

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San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, th e IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA