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Document overview
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Technical content
Features
- Fully integrated PLL
- Fourteen LVCMOS/LVTTL outputs; (12)clocks, (1)feedback, (1)sync
- Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs
- CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
- Output frequency range: 10MHz to 150MHz
- VCO range: 240MHz to 500MHz
- Output skew: 200ps (maximum)
- Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
- Full 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Compatible with PowerPC™ and Pentium™ Microprocessors
- Available in lead-free (RoHS 6)packages. 1 2 3 4 5 6 7 8 9 10 11 12 13 3233343536373839 31 30 29 28 27 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 GNDO VCO_SEL FSEL_FB1 QSYNC GNDO QC0 VDDO INV_CLK QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO GNDI VDDA nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 XTAL1 XTAL2 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 FSEL_FB0 EXT_FB GNDO QFB VDD Pin Assignment 87972I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View 87972I-147 Datasheet Low Skew, 1-to-12 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer
2©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet Block Diagram SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ D Q D Q D Q D Q D Q D Q QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC XTAL1 XTAL2 VCO_SEL PLL_SEL REF_SEL CLK_SEL EXT_FB CLK0 CLK1 Pullup Pullup Pullup Pullup Pullup Pullup Pullup FSEL_FB2 Pullup nMR/OE Pullup FSEL_A[0:1] Pullup FSEL_B[0:1] Pullup FSEL_C[0:1] Pullup FSEL_FB[0:2] Pullup FRZ_CLK Pullup FRZ_DATAPullup INV_CLK Pullup 1÷2 PHASE DETECTOR LPF VCO POWER-ON RESET OUTPUT DISABLE CIRCUITRY DATA GENERATOR SYNC PULSE ÷4, ÷6, ÷8, ÷12 ÷4, ÷6, ÷8, ÷10 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10
3©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet Simplified Block Diagram SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ SYNC FRZ OUTPUT DISABLE CIRCUITRY PLL VCO RANGE 240MHz - 500MHz SYNC FRZ INV_CLK FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12 FSEL_ A1 A0 QAx 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷10 FSEL_ B1 B0 QBx 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FSEL_ FB2 FB1 FB0 QFB 0 0 ÷2 0 1 ÷4 1 0 ÷6 1 1 ÷8 FSEL_ C1 C0 QCx nMR/OE XTAL1 XTAL2 VCO_SEL PLL_SEL REF_SEL EXT_FB CLK0 CLK1 Pullup Pullup Pullup Pullup Pullup CLK_SEL Pullup Pullup QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC0 QC1 QC2 QC3 QFB QSYNC FRZ_CLK Pullup FRZ_DATAPullup
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1 GNDI Power Power supply ground. Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs to Hi-Z and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circ uitry. LVCMOS / LVTTL interface levels. 4 FRZ_DATA Input Pullup Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels.
6 PLL_SEL Input Pullup
Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. 7 REF_SEL Input Pullup Selects between crystal and reference clock. When LOW, selects CLK0 or CLK1. When HIGH, selects crystal inputs. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 9, 10 CLK0, CLK1 Input Pullup Single-ended referenc e clock inputs. LVCMOS/LVTTL interface levels. XTAL_2 Input Crystal oscillator interface. XTAL _1 is the input. XTAL_2 is the output. 13 V DDA Power Analog supply pin. 14 INV_CLK Input Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. GNDO Power Power supply ground. QC1, QC0 Output Single-ended Bank C clock output s. LVCMOS/ LVTTL interface levels. 37, 45, 49 VDDO Power Output power supply pins. FSEL_C0 Input Pullup Select pins for Bank C outputs. LV CMOS / LVTTL interface levels. See Table 3A. 25 QYSNC Output Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. 28 V DD Power Power supply pin. 29 QFB Output Single-ended feedback clock out put. LVCMOS / LVTTL interface levels. 31 EXT_FB Input Pullup External feedback. LVCMOS / LVTTL interface levels. QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels. FSEL_B0 Input Pullup Select pins for Bank B outputs. LV CMOS / LVTTL interface levels. See Table 3A. FSEL_A0 Input Pullup Select pins for Bank A outputs. LV CMOS / LVTTL interface levels. See Table 3A. QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels. 52 VCO_SEL Input Pullup Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Table 2. Pin Characteristics
Figure 1. Timing Diagrams
7©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 42.3C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 250 mA IDDA Analog Supply Current 20 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage VCO_SEL, PLL_SEL, REF_SEL, CLK_SEL, EXT_FB, FSEL_FB[0:2], FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FRZ_DATA -0.3 0.8 V CLK0, CLK1, INV_CLK, FRZ_CLK -0.3 1.3 V I IN Input Current ±120 µA VOH Output High Voltage; NOTE 1 I OH = -20mA 2.4 V VOL Output Low Voltage; NOTE 1 I OL = 20mA 0.5 V
Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 6. Crystal Characteristics Table 7. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
9©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load AC Test Circuit Cycle-to-Cycle Jitter Static Phase Offset Output Skew Output Duty Cycle/Pulse Width Period Output Rise/Fall Time SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO VDDA, ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB ➤ ➤ t(Ø) VDD VDD t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges CLK0, CLK1 EXT_FB tsk(o) Qx Qy tPERIOD tPW tPERIOD odc = VDDO x 100% tPW QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB 0.8V 2V 2V 0.8V tR tF QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB
10©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet
Application Information
Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perform- ance, power supply isolation is required. The 87972I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin. Figure 2. Power Supply Filtering for additional protection, a 1k resistor can be tied from XTAL_IN to ground. can be tied from the CLK to ground. All unused LVCMOS output can be left floating. There should be no trace attached.
Table 8. JA vs. Air Flow Table for a 52 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 9. Package Dimensions for 52 Lead LQFP
15©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet
Ordering Information
Table 10. Ordering Information
16©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet Revision History Sheet Rev Table Page Description of Change Date A T10 Features Section - added leaf-free bullet. Added Recommendations for Unused Input/Output Pins section. Added LVCMOS to XTAL Interface section. Package Dimensions Table - added L and dimensions. Ordering Information Table - added 52 Lead LQFP ordering information; corrected non-LF marking from ICS87972DYI147 to ICS87972DYI-147. 6/5/08 A the LF note below the table. Updated datasheet format. 12/7/15
17©2015 Integrated Device Technology, Inc December 7, 2015 87972I-147 Datasheet
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