ICS87951I IDT | Alldatasheet

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87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS87951I is a low voltage, low skew 1-to-9 Differential-to-LVCMOS/LVTTL Cock Generator. The CS87951I has two selectable clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The CLK1, nCLK1 pair can accept most standard differential input levels. With output frequencies up to 180MHz, the ICS87951I is targeted for high performance clock appli- cations. Along with a fully integrated PLL, the ICS87951I con- tains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”.

  • Fully integrated PLL
  • Nine single ended 3.3V LVCMOS/LVTTL outputs
  • Selectable single ended CLK0 or differential CLK1, nCLK1 inputs
  • The single ended CLK0 input can accept the following input levels: LVCMOS or LVTTL input levels
  • CLK1, nCLK1 supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL
  • Output frequency range: 25MHz to 180MHz
  • VCO range: 200MHz to 480MHz
  • External feedback for ”zero delay” clock regeneration
  • Cycle-to-cycle jitter: ±100ps (typical)
  • Output skew: 375ps (maximum)
  • PLL reference zero delay: 350ps window (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS-compliant packages PIN A SSIGNMENT QD2 VDDO QD3 GND QD4 V DDO MR/nOE nCLK1 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 QC0 V DDO QC1 GND QD0 V DDO QD1 GND V DDA EXT_FB DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND CLK1 GND QB VDDO QA GND CLK0 PLL_SEL CLK_SEL ICS87951I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View

87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER BLOCK DIAGRAM DIV_SELA PLL_SEL CLK0 CLK_SEL nCLK1 CLK1 EXT_FB DIV_SELB DIV_SELC MR/nOE DIV_SELD QA QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 VCO 200-480MHz PHASE DETECTOR LPF Internal Pulldown Internal Pulldown Internal Pullup Internal Pulldown Internal Pulldown Internal Pulldown Internal Pulldown Internal Pulldown Internal Pulldown Internal Pulldown/ Pullup POWER-ON RESET

TABLE 1. PIN DESCRIPTIONS TABLE 2. P IN CHARACTERISTICS

87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE stupnIs tuptuO EOn/RMA QB Q1 CQ,0CQ4 DQ:0DQ 1Z iHZ iHZ iHZ iH 0d elbanEd elbanEd elbanEd elbanE TABLE 3B. OPERATING MODE FUNCTION TABLE stupnI edoMgnitarepO LES_LLP 0s sapyB 1L LP TABLE 3C. PLL INPUT FUNCTION TABLE stupnI LES_KLCt upnILLP

01 KLCn,1KLC

10 KLC

ALES_VIDB LES_VIDC LES_VIDD LES_VIDA QB Qx CQx DQ 0000 2 /OCV4 /OCV4 /OCV4 /OCV 0001 2 /OCV4 /OCV4 /OCV8 /OCV 00 10 2 /OCV4 /OCV8 /OCV4 /OCV 00 11 2 /OCV4 /OCV8 /OCV8 /OCV 01 00 2 /OCV8 /OCV4 /OCV4 /OCV 01 01 2 /OCV8 /OCV4 /OCV8 /OCV 011 0 2 /OCV8 /OCV8 /OCV4 /OCV 0111 2 /OCV8 /OCV8 /OCV8 /OCV 10 00 4 /OCV4 /OCV4 /OCV4 /OCV 10 0 1 4 /OCV4 /OCV4 /OCV8 /OCV 10 10 4 /OCV4 /OCV8 /OCV4 /OCV 10 11 4 /OCV4 /OCV8 /OCV8 /OCV 1100 4 /OCV8 /OCV4 /OCV4 /OCV 1101 4 /OCV8 /OCV4 /OCV8 /OCV 1110 4 /OCV8 /OCV8 /OCV4 /OCV 1111 4 /OCV8 /OCV8 /OCV8 /OCV TABLE 3D. P ROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE

87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER TABLE 4B. DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V ADD egatloVylppuSgolanA 531.33 .35 64.3V V ODD egatloVylppuStuptuO 531.33 .35 64.3V I ODD tnerruCylppuSrewoPV llA DD snip5 11A m I ADD tnerruCylppuSgolanA 02A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 0KLC2 V DD 3.0+V ,DLES_VID:ALES_VID ,LES_KLC,LES_LLP EOn/RM,BF_TXE 2V DD 3.0+V V LI egatloVwoLtupnI 0KLC3 .0-3 .1V ,DLES_VID:ALES_VID ,LES_KLC,LES_LLP EOn/RM,BF_TXE 3.0-8 .0V V PP kaeP-ot-kaeP egatloVtupnI 1KLCn,1KLC0 030 001V m V RMC 2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV DD 58.0-V V HO egatloVhgiHtuptuOI HO Am04-=4 .2V V LO egatloVwoLtuptuOI LO Am04=5 .0V I NI tnerruCtupnI 021±A µ VsadenifedsiegatlovedomnommoC:1ETON HI . Vsi1KLCndna1KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON ADD .V3.0+ ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDDA + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.1°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 6. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C

87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEWCYCLE-TO-CYCLE J ITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

PHASE JITTER AND STATIC PHASE OFFSET SCOPE Qx LVCMOS 1.65V±5% -1.65V±5% QA, QB, QCx, QDx ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tsk(o) VDDO VDDO 2Qy Qx VCMR Cross Points V PP GND CLK1 nCLK1 VDD Clock Outputs 0.8V 2V 2V 0.8V tR tF EXT_FB ➤ ➤t(Ø) VOH VOL VOH VOL VDDO CLK0, CLK1 nCLK1 tPW tPERIOD VDDO VDDO VDDO tPW tPERIOD odc = QA, QB, QCx, QDx VDDA, VDDO GND (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter

TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. P ACKAGE DIMENSIONS

TABLE 9. O RDERING INFORMATION the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

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87951AYI www.idt.com REV. C JULY 17, 2010 ICS87951I LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY BUFFER We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com

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San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, th e IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA