87950BYILF

87950I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
• PDF pages: 14

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Low Skew, 1-to-9 LVCMOS / LVTTL Clock Multiplier 87950I DATA SHEETPRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES NOVEMBER 2, 2016 REVISION C 11/6/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION FEATURES The 87950I is a low voltage, low skew 1-9 LVCMOS/LVTTL Clock Generator. With output frequencies up to 250MHz the 87950I is targeted for high performance clock applications. Along with a fully integrated PLL the 87950I contains frequency confi gurable outputs.

• Fully integrated PLL
• 9 single ended 3.3V LVCMOS/LVTTL outputs
• Selectable CLK or single ended crystal inputs
• Maximum output frequency: 250MHz
• Maximum VCO range: 240MHz to 500MHz
• Cycle-to-cycle jitter: ±100 (typical)
• Output skew: 375ps (maximum) all outputs @ same frequen- cy
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 87973i 0 0 VCO 240-500MHz PHASE DETECTOR LPF ÷8/÷16 Power-On Reset OSC PIN ASSIGNMENT QD2 VDDO QD3 GND QD4 V DDO MR/nOE XTAL_OUT 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 QC0 V DDO QC1 GND QD0 V DDO QD1 GND V DDA FBDIV_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD GND XTAL_IN GND QB VDDO QA GND CLK PLL_SEL CLK_SEL 87950I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View DIV_SELA PLL_SEL CLK CLK_SEL XTAL_IN XTAL_OUT FBDIV_SEL DIV_SELB DIV_SELC MR/nOE DIV_SELD QA QB QC0 QC1 QD0 QD1 QD2 QD3 QD4 BLOCK DIAGRAM Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown

2 REVISION C 11/6/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1V DDA Power Analog supply pin.

2 FBDIV_SEL Input Pulldown Selects divide value for Bank feedback output as described in

Table 3E. LVCMOS / LVTTL interface levels. 3 DIV_SELA Input Pulldown Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels. 4 DIV_SELB Input Pulldown Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels. 5 DIV_SELC Input Pulldown Selects divide value for Bank C outputs as described in Table 3D. LVCMOS / LVTTL interface levels. 6 DIV_SELD Input Pulldown Selects divide value for Bank D outputs as described in Table 3D. LVCMOS / LVTTL interface levels. 21, 25, 29 GND Power Power supply ground.

10 MR/nOE Input Pulldown

DDO Power Output supply pins. QD2, QD1, QD0 Output Bank D clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 22, 24 QC1, QC0 Output Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 26 QB Output Bank B clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 28 QA Output Bank A clock output. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. 30 CLK Input Pulldown LVCMOS / LVTTL phase detector reference clock input.

31 PLL_SEL Input Pulldown

clock. LVCMOS / LVTTL interface levels. selects XTAL_IN, XTAL _OUT. LVCMOS / LVTTL interface levels. Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 LOW SKEW, 1-TO-9

LVCMOS / LVTTL CLOCK MULTIPLIER TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Inputs Outputs MR/nOE QA QB QC0, QC1 QD0:QD4

1 HiZ HiZ HiZ HiZ

0 Enabled Enabled Enabled Enabled

TABLE 3B. OPERATING MODE FUNCTION TABLE Inputs Operating Mode PLL_SEL

0 Bypass

1 PLL

TABLE 3C. PLL INPUT FUNCTION TABLE Inputs CLK_SEL PLL Input

0 XTAL Oscillator

1 CLK

TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE FOR FBDIV-SEL Inputs FBDIV_SEL Function 1÷ 8 0 ÷16

LOW SKEW, 1-TO-9 LVCMOS / LVTTL CLOCK MULTIPLIER 87950I DATA SHEET

4 REVISION C 11/6/15

TABLE 3F. INPUT REFERENCE VS. OUTPUT FREQUENCY RELATIONSHIP Inputs Outputs DIV_SELA DIV_SELB DIV_SELC DIV_SELD FBDIV_SEL = 1 FBDIV_SEL = 0 QA QB QCx QDx QA QB QCx QDx 0000 4 x 2 x 2 x 2 x 8 x 4 x 4 x 4 x 0001 4 x 2 x 2 x x 8 x 4 x 4 x 2 x 0010 4 x 2 x x 2 x 8 x 4 x 2 x 4 x 0011 4 x 2 x x x 8 x 4 x 2 x 2 x 0100 4 x x 2 x 2 x 8 x 2 x 4 x 4 x 0101 4 x x 2 x x 8 x 2 x 4 x 2 x 0110 4 x x x 2 x 8 x 2 x 2 x 4 x 0111 4 x x x x 8 x 2 x 2 x 2 x 1000 2 x 2 x 2 x 2 x 4 x 4 x 4 x 4 x 1001 2 x 2 x 2 x x 4 x 4 x 4 x 2 x 1010 2 x 2 x x 2 x 4 x 4 x 2 x 4 x 1011 2 x 2 x x x 4 x 4 x 2 x 2 x 1100 2 x x 2 x 2 x 4 x 2 x 4 x 4 x 1101 2 x x 2 x x 4 x 2 x 4 x 2 x 1110 2 x x x 2 x 4 x 2 x 2 x 4 x 1111 2 x x x x 4 x 2 x 2 x 2 x Inputs Outputs DIV_SELA DIV_SELB DIV_SELC DIV_SELD QA QB QCx QDx

0000 VCO/2 VCO/4 VCO/4 VCO/4

0001 VCO/2 VCO/4 VCO/4 VCO/8

0010 VCO/2 VCO/4 VCO/8 VCO/4

0011 VCO/2 VCO/4 VCO/8 VCO/8

0100 VCO/2 VCO/8 VCO/4 VCO/4

0101 VCO/2 VCO/8 VCO/4 VCO/8

0110 VCO/2 VCO/8 VCO/8 VCO/4

0111 VCO/2 VCO/8 VCO/8 VCO/8

1000 VCO/4 VCO/4 VCO/4 VCO/4

1001 VCO/4 VCO/4 VCO/4 VCO/8

1010 VCO/4 VCO/4 VCO/8 VCO/4

1011 VCO/4 VCO/4 VCO/8 VCO/8

1100 VCO/4 VCO/8 VCO/4 VCO/4

1101 VCO/4 VCO/8 VCO/4 VCO/8

1110 VCO/4 VCO/8 VCO/8 VCO/4

1111 VCO/4 VCO/8 VCO/8 VCO/8

TABLE 3E. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE

5 LOW SKEW, 1-TO-9

TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 5. CRYSTAL CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C NOTE 1: Outputs terminated with 50Ω to VDDO/2. conditions for extended periods may affect product reliability.

6 REVISION C 11/6/15

TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 2: Jitter performance using Xtal inputs. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

7 LOW SKEW, 1-TO-9

LVCMOS / LVTTL CLOCK MULTIPLIER 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT PULSE WIDTH/PERIODCYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME tjit(cc) = tcycle n –tcycle n+1

1000 Cycles

PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW

LOW SKEW, 1-TO-9 LVCMOS / LVTTL CLOCK MULTIPLIER 87950I DATA SHEET

8 REVISION C 11/6/15

FIGURE 2. CRYSTAL INPUT INTERFACE resonant crystal and were chosen to minimize the ppm error. be slightly adjusted for different board layouts. FIGURE 1. POWER SUPPLY FILTERING

APPLICATION INFORMATION

XTAL_IN XTAL_OUT 18pF Parallel Cry stal 22p 22p

9 LOW SKEW, 1-TO-9

TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

10 REVISION C 11/6/15

TABLE 9. PACKAGE DIMENSIONS

11 LOW SKEW, 1-TO-9

TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

LOW SKEW, 1-TO-9 LVCMOS / LVTTL CLOCK MULTIPLIER 87950I DATA SHEET

12 REVISION C 11/6/15

Rev Table Page Description of Change Date B T10 Features Section - added Lead-Free bullet. Crystal Characteristics Table - added Drive Level. Ordering Information Table - added Lead-Free part number and note. Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the data- sheet. 6/14/05 C T10 11 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/16/10 Updated data sheet format 2/18/15 C 1 Product Discontinuation Notice - Last time buy expires November 2, 2016.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.

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