87946AYILFT

87946I RENESAS | Alldatasheet

Document overview

• Manufacturer or author: epieczon
• PDF pages: 12

Technical content

Features

• Ten single-ended LVCMOS outputs, 7 typical output impedance
• Selectable CLK0 and CLK1 LVCMOS clock inputs
• CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
• Maximum input/output frequency: 150MHz
• Output skew: 350ps (maximum)
• 3.3V input, 3.3V outputs
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For drop-in replacement use 87946i-147 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 CLK_SEL VDD CLK0 CLK1 DIV_SELA DIV_SELB DIV_SELC GND GND QB0 VDDB QB1 GND QB2 VDDB VDDC VDDC QC0 GND QC1 VDDC QC2 GND QC3 GND QA0 VDDA QA1 GND QA2 VDDA MR/nOE 87946I 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Pin AssignmentBlock Diagram CLK0 CLK_SEL CLK1 DIV_SELA QA[0:2] ÷2Pullup Pullup Pulldown Pulldown DIV_SELB DIV_SELC QC[0:3] Pulldown MR/nOE Pulldown QB[0:2] Pulldown PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer 87946I Datasheet

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE 1: VDDx denotes VDDA, VDDB, VDDC. 1 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. 2V DD Power Positive supply pin. 3, 4 CLK0, CLK1 Input Pullup LVCMOS/LVTTL clock inputs. 5 DIV_SELA Input Pulldown Controls frequency division for Bank A outputs. LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. LVCMOS/LVTTL interface levels. 24, 27, 31 GND Power Power supply ground. 9, 13, 17 V DDC Power Positive supply pins for Bank C outputs. QC2, QC3 Output Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 V DDB Power Positive supply pins for Bank B outputs. 19, 21, 23 QB2, QB1, QB0 Output Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 V DDA Power Positive supply pins for Bank A outputs. 26, 28, 30 QA2, QA1, QA0 Output Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance.

32 MR/nOE Input Pulldown

Master reset and output enable. When LOW, output drivers are enabled. When HIGH, output drivers are in High-Impedance and dividers are reset. LVCMOS / LVTTL interface levels.

Table 3. Function Table NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. NOTE 1: VDDX denotes VDDA, VDDB, VDDC.

1 X X X High-Impedance High-Impedance High-Impedance

0 X 0 X Active f IN/1 Active

0 X 1 X Active f IN/2 Active

0 X X 0 Active Active f IN/1

0 X X 1 Active Active f IN/2

4© 2016 Integrated Device Technology, Inc Revision C, September 20, 2016 87946I Datasheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDX = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE 2V DD + 0.3 V CLK0, CLK1 2 V DD + 0.3 V VIL Input Low Voltage DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V I IH Input High Current DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE VDD = VIN = 3.6V 120 µA CLK0, CLK1 V DD = VIN = 3.6V 5 µA IIL Input Low Current DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE VDD = 3.6V, VIN = 0V -5 µA CLK0, CLK1 V DD = 3.6V, VIN = 0V -120 µA VOH Output High Voltage I OH = -20mA 2.5 V VOL Output Low Voltage I OH = 20mA 0.4 V

Table 5. AC Characteristics, VDD = VDDX = 3.3V ± 0.3V, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: VDDX denotes VDDA, VDDB, VDDC. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.

6© 2016 Integrated Device Technology, Inc Revision C, September 20, 2016 87946I Datasheet Parameter Measurement Information 3.3V Output Load AC Test Circuit Multiple Frequency Skew Propagation Delay Output Skew Part-to-Part Skew Output Rise/Fall Time SCOPE Qx GND 1.65V ± 0.15V -1.65V ± 0.15V VDD, VDDA, VDDB, VDDC tsk(ω) QBx, QCx QAx t PD VDDx VDDx CLK0, CLK1 QAx, QBx, QCx t sk(o) VDDx VDDx Qx Qy t sk(pp) VDDx VDDx Part 1 Part 2 Qx Qy 0.8V 2V 2V 0.8V tR tF QAx, QBx, QCx

7©2016 Integrated Device Technology, Inc Revision C, September 20, 2016 87946I Datasheet

Application Information

Recommendations for Unused Input and Output Pins Inputs: CLK Inputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS Control Inputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. Reliability Information Table 6. JA vs. Air Flow Table NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 32 Lead LQFP

9©2016 Integrated Device Technology, Inc Revision C, September 20, 2016 87946I Datasheet

Ordering Information

Table 8. Ordering Information

10© 2016 Integrated Device Technology, Inc Revision C, September 20, 2016 87946I Datasheet Revision History Sheet Rev Table Page Description of Change Date AT 1 Features section added Max Input/Output frequency bullet. Revised MR/nOE description. Revised Output Rise & Fall time diagram 8/14/02 BT 5 4 AC Characteristics Table changed: (CLK0, CLK1) TPLH from 6.0ns max. to 12.0ns max, deleted typical value (CLK0, CLK1) TPHL from 6.0ns max. to 11.5ns max, deleted typical value 10/22/02 B AC Characteristics Table - changed symbol fOUT to fIN. Moved 150MHz min. to max. column. Added Thermal Note. Corrected NOTE 2. Updated parameter Measurement Information section. Added Recommendations for Unused Input and Output Pins section. Updated Package Outline drawing. Ordering Information Table - deleted ICS prefix from Part/Order Number column. Added lead-free marking. 3/17/10 B 1 Deleted HiperClocks logo from General Description. Update Header / Footer of the datasheet. 6/22/12 Updated data sheet format. 2/18/15 B Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer. 6/28/16 C 1 Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer. 9/20/16

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San Jose, CA 95138 USA www.IDT.com 87946I Datasheet 11©2016 Integrated Device Technology, Inc Revision C, September 20, 2016

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