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Technical content

Features

  • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance
  • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs
  • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL
  • Maximum input frequency: 250MHz
  • Bank skew: 30ps (maximum)
  • Output skew: 175ps (maximum)
  • Part-to-part skew: 850ps (maximum)
  • Multiple frequency skew: 200ps (maximum)
  • 3.3V core, 3.3V or 2.5V output supply modes
  • -40°C to 85°C ambient operating temperature
  • Lead-free packaging Block Diagram Pin Assignment 87946I-147 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View CLK0 CLK_SEL CLK1 DIV_SELA QA[0:2] Pullup Pullup Pullup Pulldown Pulldown DIV_SELB DIV_SELC QC[0:3] Pulldown MR/nOE Pulldown QB[0:2] Pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 CLK_SEL VDD CLK0 CLK1 DIV_SELA DIV_SELB DIV_SELC GND GND QB0 VDDB QB1 GND QB2 VDDB VDDC VDDC QC0 GND QC1 VDDC QC2 GND QC3 GND QA0 VDDA QA1 GND QA2 VDDA MR/nOE 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer 87946I-147 Datasheet

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. 2V DD Power Positive supply pin. 3, 4 CLK0, CLK1 Input Pullup Single-ended clock inputs. LVCMOS/LVTTL interface levels. LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. See Table 3. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. See Table 3. LVCMOS/LVTTL interface levels. 24, 27, 31 GND Power Power supply ground. 9, 13, 17 V DDC Power Output supply pins for Bank C outputs. QC2, QC3 Output Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 V DDB Power Output supply pins for Bank B outputs. QB1, QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 V DDA Power Output supply pins for Bank A outputs. QA1, QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance.

32 MR/nOE Input Pulldown

logic LOW, the internal dividers and the outputs are enabled. See Table 3. LVCMOS/LVTTL interface levels.

Table 3. Clock Input Function Table AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

1 X X X High-Impedance High-Impedance High-Impedance

0 X 0 X Active f IN/1 Active

0 X 1 X Active f IN/2 Active

0 X X 0 Active Active f IN/1

0 X X 1 Active Active f IN/2

4©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA, VDDB, VDDC Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 55 mA IDDA, IDDB, IDDC Output Supply Current 22 mA Symbol Parameter Test Conditi ons Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V I IH Input High Current MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL V DD = VIN = 3.6V 150 µA CLK0, CLK1 V DD = VIN = 3.6V 5 µA IIL Input Low Current MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = 3.6V, VIN = 0V -5 µA CLK0, CLK1 V DD = 3.6V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 V DDA = VDDB = VDDC = 3.6V 2.6 V VOL Output Low Voltage; NOTE 1 V DDA = VDDB = VDDC = 3.63V 0.5 V IOZL Output Hi-Z Current Low V DDA = VDDB = VDDC = 3.63V -5 µA IOZH Output Hi-Z Current High V DDA = VDDB = VDDC = 3.63V 5 µA

5©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Table 4D. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V IIH Input High Current MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL V DD = VIN = 3.465V 150 µA CLK0, CLK1 V DD = VIN = 3.465V 5 µA IIL Input Low Current MR/nOE, DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL VDD = 3.465V, VIN = 0V -5 µA CLK0, CLK1 V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDA = VDDB = VDDC = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 V DDA = VDDB = VDDC = 2.625V 0.5 V IOZL Output Hi-Z Current Low V DDA = VDDB = VDDC = 2.625V -5 µA IOZH Output Hi-Z Current High V DDA = VDDB = VDDC = 2.625V 5 µA

6©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Table 5A. AC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 0.3V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 ƒ  250MHz 2 5 ns tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at V DDX/2 30 ps tsk(o) Output Skew; NOTE 3, 7 M easured on rising edge at VDDX/2 175 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 275 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 850 ps tR / tF Output Rise/Fall Time; NOTE 6 20% to 80% 400 950 ps tPW Output Pulse Width t PERIOD/2 - 1 t PERIOD/2 t PERIOD/2 + 1 % tEN Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns

7©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 ƒ  250MHz 2 5 ns tsk(b) Bank Skew, NOTE 2, 7 Measured on rising edge at V DDX/2 35 ps tsk(o) Output Skew; NOTE 3, 7 M easured on rising edge at VDDX/2 175 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 200 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at VDDX/2 875 ps tR / tF Output Rise/Fall Time; NOTE 6 20% to 80% 400 950 ps tPW Output Pulse Width t PERIOD/2 - 1 t PERIOD/2 t PERIOD/2 + 1 % tEN Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns

8©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Parameter Measurement Information 3.3V Core/3.3V Output Load AC Test Circuit Output Skew Bank Skew 3.3V Core/2.5V Output Load AC Test Circuit Part-to-Part Skew Multiple Frequency Skew SCOPE Qx GND 1.65V±0.15V -1.65V±0.15V VDD, VDDA, VDDB, VDDC t sk(o) VDDO VDDO Qx Qy t sk(b) VDDx VDDx Where X = Bank A, B or C QX0:QXx QX0:QXx SCOPE Qx GND -1.25V± 5% VDD 1.25V± 5% 2.05V± 5% VDDA, VDDB, VDDC t sk(pp) VDDO VDDO Part 1 Part 2 Qx Qy tsk(ω) QBx, QCx QAx

9©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Parameter Measurement Information, continued tPW & tPERIOD Output Rise/Fall Time Propagation Delay tPW tPERIOD VDDx VDDx VDDx tPW tPERIOD odc = QAx, QBx, QCx 20% 80% 80% 20% tR tF QAx, QBx, QCx t PD VDDx VDDx CLK0, CLK1 QAx, QBx, QCx

resistor can be tied from the CLK input to ground. Table 6. JA vs. Air Flow Table for a 32-Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 32-Lead LQFP

12©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet

Ordering Information

Table 8. Ordering Information

13©2016 Integrated Device Technology, Inc. Revision C, September 19, 2016 87946I-147 Datasheet Revision History Sheet Rev Table Page Description of Change Date A Features section added Lead-Free bullet. Pin Description Table - corrected description for V DDA, VDDB and VDDC. Parameter Measurement Information Section - added part-to-part skew, bank skew, and multiple frequency skew diagrams. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free marking. Updated format throughout the datasheet. 7/22/08 A T5A - T5B 6 - 7 AC Tables - added thermal note. Ordering Information Table - corrected the Part/Order Numbers and corrected the non-LF marking. Updated Header/Footer of the datasheet. 8/7/09 A T8 12 Removed leaded orderable parts from Ordering Information table 11/15/12 A T8 12 Ordering Information Table - Added 87946AYI-147LF/W Ordering option. Updated Technical Support Contact Info to: clocks@idt.com 4/30/14 B 3 Absolute Maximum Ratings Table - added Junction Temperature. Updated datasheet header/footer. Deleted “ICS” prefix from part number. 2/24/16 C 1 Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer.

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