87946I-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: epieczon
  • PDF pages: 16

Technical content

Features

  • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance
  • LVPECL clock input pair
  • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL
  • Maximum input frequency: 250MHz
  • Output skew: 120ps (maximum)
  • Part-to-part skew: 700ps (maximum)
  • Multiple frequency skew: 320ps (maximum)
  • Additive phase jitter, RMS: 0.19ps (typical)
  • 3.3V core, 3.3V or 2.5V output supply modes-40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • For functional replacement use 87946i-147 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nc VDD PCLK nPCLK DIV_SELA DIV_SELB DIV_SELC GND GND QB0 VDDB QB1 GND QB2 VDDB VDDC VDDC QC0 GND QC1 VDDC QC2 GND QC3 GND QA0 VDDA QA1 GND QA2 VDDA MR/nOE 87946I-01 32-Lead LQFP 7mm x 7mm x 1.45mm package body Y Package Top View Pin Assignment Block Diagram PCLK nPCLK DIV_SELA QA0:QA 2 Pullup Pulldown Pullup Pulldown Pulldown DIV_SELB DIV_SELC QC0:QC 3 Pulldown MR/nOE Pulldown QB0:QB 2 Pulldown PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 87946I-01 Datasheet 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 3 PCLK Input Pulldown Non- inverting differential LVPECL clock input. 4 nPCLK Input Pullup Inverting differential LVPECL clock input. LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. See Table 3. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. See Table 3. LVCMOS/LVTTL interface levels. 20, 24, 27, 31 GND Power Power supply ground. 9, 13, 17 V DDC Power Output supply pins for Bank C outputs. QC2, QC3 Output Single-ended Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 V DDB Power Output supply pins for Bank B outputs. QB0 Output Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 V DDA Power Output supply pins for Bank A outputs. QA0 Output Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance.

32 MR/nOE Input Pulldown

the internal dividers are reset and the outputs are High-Impedance (Hi-Z). Table 3. LVCMOS/LVTTL interface levels.

Table 3. Clock Input Function Table NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability.

1 X X X High-Impedance High-Impedance High-Impedance

0 X 0 X Active fIN/1 Active

0 X 1 X Active fIN/2 Active

0 X X 0 Active Active fIN/1

0 X X 1 Active Active fIN/2

4©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Table 4B. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Information section. Load Test Circuit diagrams. Table 4D. LVPECL DC Characteristics, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA, VDDB, VDDC Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 54 mA IDDA, IDDB, IDDC Output Supply Current 22 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage V DD = 3.465V 2 V DD + 0.3 V VIL Input Low Voltage V DD = 3.465V -0.3 0.8 V IIH Input High Current V DD = VIN = 3.465V 150 µA IIL Input Low Current V DD = 3.465V, VIN = 0V -5 µA VOH OUtput High Voltage; NOTE 1 V DDA = VDDB = VDDC = 3.465V 2.6 V VOL Output Low Voltage; NOTE 1 V DDA = VDDB = VDDC = 3.465V or 2.525V 0.5 V IOZL Output Hi-Z Current Low -5 µA IOZH Output Hi-Z Current High 5µ A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current PCLK V DD = VIN = 3.465V 150 µA nPCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current PCLK V DD = 3.465V, VIN = 0V -5 µA nPCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1 GND + 1.5 V DD V

5©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Table 5A. AC Characteristics, VDD = VDDA = VDDB = VDDC = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to VDDX/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = 3.3V ± 5%, VDDA = VDDB = VDDC = 2.5V ± 5%, TA = -40°C to 85°C For NOTES, please see Table 5A above. Symbol Parameter Test Conditio ns Minimum Typic al Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 ƒ  250MHz 2.3 3.1 3.8 ns tsk(b) Bank Skew, NOTE 2, 7 Meas ured on rising edge at VDDX/2 30 ps tsk(o) Output Skew; NOTE 3, 7 M easured on rising edge at VDDX/2 130 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 320 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at V DDX/2 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 125MHz, 12kHz – 20MHz 0.19 ps tR / tF Output Rise/Fall Time 20% to 80% 400 950 ps odc Output Duty Cycle 40 50 60 % t EN Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tPD Propagation Delay; NOTE 1 ƒ  250MHz 2.5 3.2 3.8 ns tsk(b) Bank Skew, NOTE 2, 7 Meas ured on rising edge at VDDX/2 35 ps tsk(o) Output Skew; NOTE 3, 7 M easured on rising edge at VDDX/2 120 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDX/2 325 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 Measured on rising edge at V DDX/2 700 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 125MHz, 12kHz – 20MHz 0.19 ps tR / tF Output Rise/Fall Time 20% to 80% 350 800 ps odc Output Duty Cycle 40 50 57 % t EN Output Enable Time; NOTE 6 ƒ = 10MHz 3 ns tDIS Output Disable Time; NOTE 6 ƒ = 10MHz 3 ns

6©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 125MHz 12kHz to 20MHz = 0.19ps (typical) SSB Phase Noise dBc/Hz Offset Frequency (Hz)

7©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Parameter Measurement Information 3.3V Output Load AC Test Circuit Differential Input Level Bank Skew 3.3V/2.5V Output Load AC Test Circuit Output Skew Multiple Frequency Skew SCOPE Qx GND 1.65V¬±5 1.65V¬±5 VDD, VDDA, VDDB, VDDC nPCLK PCLK GND VDD VCMR Cross Points VPP Where X = Bank A, B or C t sk(b) VDDx VDDx QX0:QXx QX0:QXx SCOPE Qx GND -1.25V¬±5 VDDA, VDDB, VDDC VDD 1.25V¬±5 2.05V¬±5 t sk(o) VDDO VDDO Qx Qy tsk(ω) QBx, QCx QAx

8©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Parameter Measurement Information, continued Part-to-Part Skew Output Rise/Fall Time Propagation Delay Output Duty Cycle/Pulse Width/Period t sk(pp) VDDO VDDO Part 1 Part 2 Qx Qy 20% 80% 80% 20% tR tF QAx, QBx, QCx nPCLK PCLK QAx, QBx, QCx t PD VDDx QAx, QBx, QCx tPERIOD tPW tPERIOD odc = x 100% tPW

Table 6. JA vs. Air Flow Table for a 32 Lead LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 7. Package Dimensions for 32 Lead LQFP

13©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet

Ordering Information

Table 8. Ordering Information

14©2015 Integrated Device Technology, Inc. Revision C, September 20, 2016 87946I-01 Datasheet Revision History Sheet Rev Table Page Description of Change Date B T5A & T5B Features section added Additive Phase Jitter and Lead-Free bullets AC Characteristics Tables - added Additive Phase Jitter row. Added Additive Phase Jitter section. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Part/Order Number and Note. Updated format throughout the datasheet. 5/4/07 Updated header/footer of datasheet. 11/10/09 Updated data sheet format. 7/21/15 B Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer. 6/28/16 C 1 Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer. 9/20/16

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