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Technical content
Features
- One differential LVDS output pair and one differential feedback output pair
- One differential clock input pair
- CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL
- Input frequency range: 62.5MHz to 1GHz
- Output frequency range: 62.5MHz to 1GHz
- VCO range: 500MHz - 1GHz
- External feedback for "zero delay" clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Cycle-to-cycle jitter: 35ps (maximum)
- Static phase offset: ±100ps
- Full 3.3V supply mode
- -40°C to 85°C ambient operating temperature
- Available in lead-free packages 874S02I 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View Block Diagram Pin Assignment 1:1 Differential-to-LVDS Zero Delay Clock Generator 874S02I Data Sheet
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
enabled. LVCMOS / LVTTL interface levels. with “Zero Delay.” Connect to pin 8.
5 FB_IN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9. SEL0, SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. DDO Power Output supply pins. 8, 9 nQFB, QFB Output Differential feedba ck output pair. HSTL interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ, Q Output Differential clock output pair. HSTL interface levels. DDA Power Analog supply pin.
17 PLL_SEL Input Pullup
dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. 18 V DD Power Core supply pin.
3©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Function Tables Table 3A. Control Input Function Table *NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz. Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/nQ 0000 5 0 0 - 1000 ÷1 0001 2 5 0 - 5 0 0 ÷ 1 0010 1 2 5 - 2 5 0 ÷ 1 0011 6 2 . 5 - 1 2 5 ÷ 1 0100 5 0 0 - 1000 ÷2 0101 2 5 0 - 5 0 0 ÷ 2 0110 1 2 5 - 2 5 0 ÷ 2 0111 5 0 0 - 1000 ÷4 1000 2 5 0 - 5 0 0 ÷ 4 1001 5 0 0 - 1000 ÷8 1010 2 5 0 - 5 0 0 x 2 1011 1 2 5 - 2 5 0 x 2 1100 6 2 . 5 - 1 2 5 x 2 1101 1 2 5 - 2 5 0 x 4 1110 6 2 . 5 - 1 2 5 x 4 1111 6 2 . 5 - 1 2 5 x 8
4©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q/nQ 0 z 000 ÷ 4 0001 ÷ 4 0010 ÷ 4 0011 ÷ 8 0100 ÷ 8 0101 ÷ 8 0110 ÷ 1 6 0111 ÷ 1 6 1000 ÷ 3 2 1001 ÷ 6 4 1010 ÷ 2 1011 ÷ 2 1100 ÷ 4 1101 ÷ 1 1110 ÷ 2 1111 ÷ 1
5©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 64.7°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.20 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 97 mA IDDA Analog Supply Current 20 mA IDDO Output Supply Current 40 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current MR, SEL[0:3] V DD = VIN = 3.465V 150 µA PLL_SEL V DD = VIN = 3.465V 10 µA IIL Input Low Current MR, SEL[0:3] V DD = 3.465V, VIN = 0V -10 µA PLL_SEL V DD = 3.465V, VIN = 0V -150 µA
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. and the input reference frequency is stable. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
7©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Static Phase Offset Output Rise/Fall Time Differential Input Level Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period 3.3V ±5% VDDA VDD, VDDO nCLK CLK nFB_IN FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges) 20% 80% 80% 20% tR tF VOD Q, QFB nQ, nQFB VDD nCLK CLK GND VCMR Cross Points VPP tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
nQ, nQFB Q, QFB Q, QFB nQ, nQFB
8©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup
Application Information
Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
12©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. The 100 differential output traces should have the same length. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. Make sure no other signal traces are routed between the clock trace pair. The series termination resistors should be located as close to the driver pins as possible. Figure 5B. PCB Board Layout for 874S02I
100 Ohm
This section provides information on power dissipation and junction temperature for the 874S02I. Equations and example calculations are also provided. The total power dissipation for the 874S02I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 64.7°C/W per Table 7 below. of board (single layer or multi-layer). Table 7. Thermal Resistance JA for 20 Lead SOIC, Forced Convection
Table 8. JA vs. Air Flow Table for a 20 Lead SOIC
300 Millimeters
15©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet
Ordering Information
Table 10. Ordering Information
16©2016 Integrated Device Technology, Inc January 26, 2016 874S02I Data Sheet Revision History] Revision Date Description of Change January 26, 2016 ▪ Removed ICS from the part number where needed. ▪ General Description - Removed ICS Chip and HiPerClockS. ▪ Ordering Information - removed quantity from tape and reel. ▪ Updated data sheet header and footer.
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San Jose, CA 95138 USA www.IDT.com 874S02I Data Sheet