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Technical content
Features
- One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair
- Differential CLK, nCLK input pair
- CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
- Output frequency range: 31.25MHz to 700MHz
- Input frequency range: 31.25MHz to 700MHz
- VCO range: 250MHz to 700MHz
- External feedback for “zero delay” clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Cycle-to-cycle jitter: 30ps (maximum)
- Output skew: 40ps (maximum)
- Static phase offset: 25ps ± 125ps
- Full 3.3V supply voltage
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- For functional replacement part use 8T49N285 QFB nQFB VDDO SEL2 FB_IN nFB_IN MR nCLK CLK GND SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q nQ VDDO 8745BI-21 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View Block Diagram PLL_SEL CLK CLK FB_IN FB_IN SEL0 SEL1 SEL2 SEL3 MR Q Q QFB QFB PLL 1:2, 1:4, 1:8 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 Pullup Pullup Pulldown Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pin Assignments PR OPOSE DICS8745BI-21
32 Lead VFQFN
5mm x 5mm x 0.925mm package body K Package Top View 8745BI-21 Datasheet 1:1 Differential-to-LVDS Zero Delay Clock Generator
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. SEL0 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 7, 11 V DDO Power Output supply pins. 8, 9 nQFB/QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ/Q Output Differential output pair. LVDS interface levels. DDA Power Analog supply pin. dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. 18 V DD Power Core supply pin.
3©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Function Tables Table 3A. Control Input Function Table *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q, nQ 0000 2 5 0 - 7 0 0 ÷ 1 0001 1 2 5 - 3 5 0 ÷ 1 0010 6 2 . 5 - 1 7 5 ÷ 1 0011 3 1 . 2 5 - 8 7 . 5 ÷ 1 0100 2 5 0 - 7 0 0 ÷ 2 0101 1 2 5 - 3 5 0 ÷ 2 0110 6 2 . 5 - 1 7 5 ÷ 2 0111 2 5 0 - 7 0 0 ÷ 4 1000 1 2 5 - 3 5 0 ÷ 4 1001 2 5 0 - 7 0 0 ÷ 8 1010 1 2 5 - 3 5 0 x 2 1011 6 2 . 5 - 1 7 5 x 2 1100 3 1 . 2 5 - 8 7 . 5 x 2 1101 6 2 . 5 - 1 7 5 x 4 1110 3 1 . 2 5 - 8 7 . 5 x 4 1111 3 1 . 2 5 - 8 7 . 5 x 8
4©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q, nQ 0000 ÷ 4 0001 ÷ 4 0010 ÷ 4 0011 ÷ 8 0100 ÷ 8 0101 ÷ 8 0110 ÷ 1 6 0111 ÷ 1 6 1000 ÷ 3 2 1001 ÷ 6 4 1010 ÷ 2 1011 ÷ 2 1100 ÷ 4 1101 ÷ 1 1110 ÷ 2 1111 ÷ 1
5©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA
20 Lead SOIC package
32 Lead VFQFN package
46.2C/W (0 lfpm) 37C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 128 mA IDDA Analog Supply Current 18 mA IDDO Output Supply Current 62 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SEL[0:3], MR V DD = VIN = 3.465V 150 µA PLL_SEL V DD = VIN = 3.465V 5 µA IIL Input Low Current SEL[0:3], MR V DD = 3.465V, VIN = 0V -5 µA PLL_SEL V DD = 3.465V, VIN = 0V -150 µA PROPOSED
NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. the PLL is locked and the input reference frequency is stable. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
8©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Phase Jitter and Static Phase Offset Cycle-to-Cycle Jitter Differential Input Level Output Skew Output Rise/Fall Time SCOPE Q nQ 3.3V±5% POWER SUPPL Y +–Float GND VDDA, VDDO VDD, nCLK CLK nFB_IN FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Q nQ nCLK CLK VDD GND VCMR Cross Points VPP Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD Q nQ
9©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Parameter Measurement Information, continued Output Duty Cycle Offset Voltage Setup Propagation Delay Differential Output Voltage Setup Q nQ nQ Q nCLK CLK tPD
resistance is not required but can be added for additional protection. additional protection, a 1k resistor can be tied from CLK to ground. at the receiver and a 100 differential transmission line environment. Figure 4. Typical LVDS Driver Termination
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
14©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Schematic Example The schematic of the 8745BI-21 layout example is shown in Figure 6A. The 8745BI-21 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. Figure 6A. 8745BI-21 LVDS Zero Delay Buffer Schematic Example SEL2 PLL_SEL RD6 SP RD4 SP 100 VDD RU3 SP = Space (i.e. not intstalled) SEL0 SEL3 RU4 SEL[3:0] = 0101, Divide by 2 RD7 (77.76 MHz) VDDO VDD 0.1uF Bypass capacitors located near the power pins RU5 SP C16 10u SEL3 VDDO (U1-7) Zo = 50 Ohm VDDA 3.3V PECL Driver SEL1 VDD=3.3V VDDO R10 SEL0 Zo = 50 Ohm RD5 C11 0.01u (U1-11) 0.1uF SEL2 (155.52 MHz) LVDS_input Zo = 100 Ohm Differential 100 SEL1 RU7 SP 0.1uF PLL_SEL ICS8745B-21 10 11 CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND VDDO nQ Q GND SEL3 VDDA SEL1 SEL0 VDDI PLL_SEL RD3 SP VDD VDDO=3.3V RU6 3.3V
15©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet The following component footprints are used in this layout example. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.
- The differential 50 output traces should have the same length.
- Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
- Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
- To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
- Make sure no other signal traces are routed between the clock trace pair.
- The matching termination resistors should be located as close to the receiver input pins as possible. Figure 6B. PCB Board Layout for 8745BI-21
100 Ohm
16©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Power Considerations This section provides information on power dissipation and junction temperature for the 8745BI-21. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8745BI-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (128mA + 18mA) = 506mW
- Power (outputs) MAX = VDDO_MAX * IDDO_MAX = 3.465V * 62mA = 215mW Total Power_MAX = 506mW + 215mW = 721mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 46.2°C/W per Table 7A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7A. Thermal Resistance JA for 20 Lead SOIC, Forced Convection Table 7B. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W PROPOS ED
17©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Reliability Information Table 8A. JA vs. Air Flow Table for a 20 Lead SOIC Table 8B. JA vs. Air Flow Table for a 32 Lead VFQFN Transistor Count The transistor count for 8745BI-21 is: 2772 Package Outline and Package Dimensions Package Outline - M Suffix for 20 Lead SOIC Table 9A. Package Dimensions for 20 Lead SOIC Reference Document: JEDEC Publication 95, MS-013, MS-119 JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. JA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W
300 Millimeters
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 2.65 A1 0.10 A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 Basic H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 0° 7° PROPOSED
18©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN Table 9B. Package Dimensions Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 9B. To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR Anvil Singulation N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 00 . 0 5 A3 0.25 Ref. b 0.18 0.25 0.30 ND & NE 8 D & E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 PROP OS ED
19©2017 Integrated Device Technology, Inc. Revision E, January 10, 2017 8745BI-21 Datasheet
Ordering Information
Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. PD max limit from 3.9ns to 4.0ns. Added Recommendations for Unused Input & Output Pins. Added Power Considerations section. Updated format throughout the datasheet. Pin Assignment - corrected lineup of pin names. Control Input Function Table - deleted “z” from 1st row of SEL3 column. Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Power Supply Filtering Technique - updated paragraph. Updated Differential Clock Input Interface. Updated Header/Footer of datasheet. Added 32 Lead VFQFN proposed pin assignment. Absolute Maximum Ratings - added 32 Lead VFQN Package Thermal Impedance. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated LVDS Output Termination. Added VFQFN EPad Thermal Release section. Added proposed 32 Lead VFQFN Thermal Resistance table. Added proposed 32 Lead VFQFN theta ja table. Added proposed 32 Lead VFQFN Package Outline and Dimensions. Ordering Information Table added proposed 32 Lead VFQFN ordering information. D1 Product Discontinuation Notice - Last time buy expires November 2, 2016.
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