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Technical content

Features

  • One differential LVDS output designed to meet or exceed the requirements of ANSI TIA/EIA-644 One differential feedback output pair
  • Differential CLK, nCLK input pair
  • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Output frequency range: 31.25MHz to 700MHz
  • Input frequency range: 31.25MHz to 700MHz
  • VCO range: 250MHz to 700MHz
  • External feedback for “zero delay” clock regeneration with configurable frequencies
  • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
  • Cycle-to-cycle jitter: 30ps (maximum)
  • Output skew: 35ps (maximum)
  • Static phase offset: 25ps ± 125ps
  • Full 3.3V supply voltage
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package QFB nQFB VDDO SEL2 FB_IN nFB_IN MR nCLK CLK GND SEL1 SEL0 VDD PLL_SEL VDDA SEL3 GND Q nQ VDDO 8745B-21 20-Lead SOIC 7.5mm x 12.8mm x 2.3mm package body M Package Top View Block Diagram PLL_SEL CLK nCLK FB_IN nFB_IN SEL0 SEL1 SEL2 SEL3 MR Q nQ QFB nQFB PLL 1:2, 1:4, 1:8 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 Pullup Pullup Pulldown Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown Pin Assignment

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.

3 MR Input Pulldown

causing the true output Q to go low and the inverted output nQ to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. SEL0 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. DDO Power Output supply pins. 8, 9 nQFB/QFB Output Differential feedback output pair. LVDS interface levels. 10, 14 GND Power Power supply ground. 12, 13 nQ/Q Output Differential output pair. LVDS interface levels. DDA Power Analog supply pin. dividers. When LOW, selects reference clock. LVCMOS/LVTTL interface levels. 18 V DD Power Core supply pin.

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 3 Rev D 2/17/15 8745B-21 DATA SHEET Function Tables Table 3A. Control Input Function Table *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q, nQ 0000 2 5 0 - 7 0 0 ÷ 1 0001 1 2 5 - 3 5 0 ÷ 1 0010 6 2 . 5 - 1 7 5 ÷ 1 0011 3 1 . 2 5 - 8 7 . 5 ÷ 1 0100 2 5 0 - 7 0 0 ÷ 2 0101 1 2 5 - 3 5 0 ÷ 2 0110 6 2 . 5 - 1 7 5 ÷ 2 0111 2 5 0 - 7 0 0 ÷ 4 1000 1 2 5 - 3 5 0 ÷ 4 1001 2 5 0 - 7 0 0 ÷ 8 1010 1 2 5 - 3 5 0 x 2 1011 6 2 . 5 - 1 7 5 x 2 1100 3 1 . 2 5 - 8 7 . 5 x 2 1101 6 2 . 5 - 1 7 5 x 4 1110 3 1 . 2 5 - 8 7 . 5 x 4 1111 3 1 . 2 5 - 8 7 . 5 x 8

Rev D 2/17/15 4 1:1 DIFFERENTIAL-TO- LVDS ZERO DELAY CLOCK GENERATOR 8745B-21 DATA SHEET Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q, nQ 0000 ÷ 4 0001 ÷ 4 0010 ÷ 4 0011 ÷ 8 0100 ÷ 8 0101 ÷ 8 0110 ÷ 1 6 0111 ÷ 1 6 1000 ÷ 3 2 1001 ÷ 6 4 1010 ÷ 2 1011 ÷ 2 1100 ÷ 4 1101 ÷ 1 1110 ÷ 2 1111 ÷ 1

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 5 Rev D 2/17/15 8745B-21 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 46.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 125 mA IDDA Analog Supply Current 17 mA IDDO Output Supply Current 59 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SEL[0:3], MR V DD = VIN = 3.465V 150 µA PLL_SEL V DD = VIN = 3.465V 5 µA IIL Input Low Current SEL[0:3], MR V DD = 3.465V, VIN = 0V -5 µA PLL_SEL V DD = 3.465V, VIN = 0V -150 µA

NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 5. Input Frequency Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C

Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. the PLL is locked and the input reference frequency is stable. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.

Rev D 2/17/15 8 1:1 DIFFERENTIAL-TO- LVDS ZERO DELAY CLOCK GENERATOR 8745B-21 DATA SHEET Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Phase Jitter and Static Phase Offset Cycle-to-Cycle Jitter Differential Input Level Output Skew Output Rise/Fall Time SCOPE Q nQ 3.3V±5% POWER SUPPL Y +–Float GND VDDA, VDDO VDD, nCLK CLK nFB_IN FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

Q nQ nCLK CLK VDD GND VCMR Cross Points VPP Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD Q nQ

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 9 Rev D 2/17/15 8745B-21 DATA SHEET Parameter Measurement Information, continued Output Duty Cycle Offset Voltage Setup Propagation Delay Differential Output Voltage Setup Q nQ nQ Q nCLK CLK tPD

resistance is not required but can be added for additional protection. additional protection, a 1k resistor can be tied from CLK to ground. recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 13 Rev D 2/17/15 8745B-21 DATA SHEET Schematic Example The schematic of the 8745B-21 layout example is shown in Figure 5A. The 8745B-21 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. Figure 5A. 8745B-21 LVDS Zero Delay Buffer Schematic Example SEL2 PLL_SEL RD6 SP RD4 SP 100 VDD RU3 SP = Space (i.e. not intstalled) SEL0 SEL3 RU4 SEL[3:0] = 0101, Divide by 2 RD7 (77.76 MHz) VDDO VDD 0.1uF Bypass capacitors located near the power pins RU5 SP C16 10u SEL3 VDDO (U1-7) Zo = 50 Ohm VDDA 3.3V PECL Driver SEL1 VDD=3.3V VDDO R10 SEL0 Zo = 50 Ohm RD5 C11 0.01u (U1-11) 0.1uF SEL2 (155.52 MHz) LVDS_input Zo = 100 Ohm Differential 100 SEL1 RU7 SP 0.1uF PLL_SEL ICS8745B-21 10 11 CLK nCLK MR nFB_IN FB_IN SEL2 VDDO nQFB QFB GND VDDO nQ Q GND SEL3 VDDA SEL1 SEL0 VDDI PLL_SEL RD3 SP VDD VDDO=3.3V RU6 3.3V

Rev D 2/17/15 14 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 8745B-21 DATA SHEET The following component footprints are used in this layout example. All the resistors and capacitors are size 0603. Power and Grounding Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces.  The differential 50  output traces should have the same length.  Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.  Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.  To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.  Make sure no other signal traces are routed between the clock trace pair.  The matching termination resistors should be located as close to the receiver input pins as possible. Figure 5B. PCB Board Layout for 8745B-21

100 Ohm

This section provides information on power dissipation and junction temperature for the 8745B-21. Equations and example calculations are also provided. The total power dissipation for the 8745B-21 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7below. Table 7. Thermal Resistance JA for 20 Lead SOIC, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Table 8. JA vs. Air Flow Table for a 20 Lead SOIC NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

300 Millimeters

1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 17 Rev D 2/17/15 8745B-21 DATA SHEET

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Rev D 2/17/15 18 1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR 8745B-21 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date B T4D 5 LVDS DC Characteristics Table - m odified VOS 0.90V min. to 1.05V min, B T9 Added Lead-Free bullet. Ordering Information Table - added Lead-Free part and note. 12/2/04 C T6 7 AC Characteristics Table - changed tPD max limit from 3.7ns to 4.0ns. Added Recommendations for Unused Input & Output Pins. Added Power Considerations section. Updated format throughout the datasheet. 4/17/07 D T4C T10 Pin Assignment - corrected lineup of pin names. Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Power Supply Filtering Technique - updated paragraph. Updated Differential Clock Input Interface. Ordering Information Table - added “LF” marking. Deleted “ICS” prefix in Part/Order number column. Updated Header/Footer of datasheet. 1/25/10 Updated Datasheet format 2/17/15

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