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Technical content
Features
- One differential input LVPECL reference clock
- Differential pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Integrated input termination resistors
- One bank of three LVPECL outputs (÷1 frequency-divided)
- One bank of three LVPECL outputs (÷4 frequency-divided)
- One bank of two LVPECL outputs (÷4 frequency-divided)
- Two banks of three LVDS outputs (÷4 frequency-divided)
- One bank of six LVDS outputs (÷4 frequency-divided)
- Total of twenty differential clock outputs
- Maximum input frequency: 650MHz
- Maximum output frequency: 650MHz (÷1 outputs)
- Maximum output frequency: 162.5MHz (÷4 outputs)
- LVCMOS interface levels for all control inputs
- Output skew: 70ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Full 2.5V supply voltage
- Available in lead-free (RoHS 6) package
- -40°C to 85°C ambient operating temperature Block Diagram 50 50 fREF CLK nCLK VT VREF CLK_EN Pullup Pullup Pullup Pullup Pullup Pullup Pullup QA[0:2] nQA[0:2] (LVPECL) QB[0:2] nQB[0:2] (LVPECL) QC[0:1] nQC[0:1] (LVPECL) QD[0:2] nQD[0:2] (LVDS) VEE VCCOA QA0 QA1 nQA1 QA2 nQA2 nQA0 CLK_EN nQB0 QB0 QB1 nQB1 QB2 nQB2 VCCOB nQC1 QC1 nQC0 VCCOC QC0 OEF OEE OED OEA VCC OEC nCLK VREF VT CLK OEB VEE VCCODE QD2 VCCODE QE0 nQE0 QE1 nQE1 QE2 nQE2 QD0 VEE nQD0 QD1 nQD1 nQD2 VCCOF nQF5 QF5 nQF4 QF4 nQF3 QF3 nQF2 VEE QF2 nQF1 QF1 nQF0 VCCOF QF0 VEE 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Assignment ICS874328I-01 64-Lead TQFP , E-Pad 10mm x 10mm x 1.0mm package body Y package Top View 874328I-01 Data Sheet 2.5V Differential Clock Divider/Buffer
Table 1. Pin Descriptions 1, 17, 32, 49, 64 V EE Power Negative supply pins. 2V CCOA Power Output power supply for Bank A outputs. 3, 4 QA0, nQA0 Output Differential Bank A output pair. LVPECL interface levels. 5, 6 QA1, nQA1 Output Differential Bank A output pair. LVPECL interface levels. 7, 8 QA2, nQA2 Output Differential Bank A output pair. LVPECL interface levels. 9, 10 QB0, nQB0 Output Differential Bank B output pair. LVPECL interface levels. 11, 12 QB1, nQB1 Output Differential Bank B output pair. LVPECL interface levels. 13, 14 QB2, nQB2 Output Differential Bank B output pair. LVPECL interface levels. 15 V CCOB Power Output power supply for Bank B outputs. 16 CLK_EN Input Pullup Clock enable. See Table 3G for function. LVCMOS/LVTTL interface levels. 18, 31 V CCODE Power Output power supply for Bank D and E outputs. 19, 20 QE0, nQE0 Output Differential Bank E output pair. LVDS interface levels. 25, 26 QD0, nQD0 Output Differential Bank D output pair. LVDS interface levels. 27, 28 QD1, nQD1 Output Differential Bank D output pair. LVDS interface levels. 29, 30 QD2, nQD2 Output Differential Bank D output pair. LVDS interface levels. 33 OEA Input Pullup Output enable for Bank A outputs. See Table 3A for function. LVCMOS/LVTTL interface levels. 34 OEB Input Pullup Output enable for Bank B outputs. See Table 3B for function. LVCMOS/LVTTL interface levels. 35 CLK Input Non-inverting differential LVPECL clock input.
36 V T
Input for termination. Both CLK and nCLK inputs are terminated to this pin. See input termination information in the applications section.
37 V REF Output
the VREF output to VT if the differential input pair CLK, nCLK is AC-coupled. input termination information in the applications section. 38 nCLK Input Inverting differential LVPECL clock input. 39 OEC Input Pullup Output enable for Bank C outputs. See Table 3C for function. LVCMOS/LVTTL interface levels. 40 V CC Power Power supply pin. 41 OED Input Pullup Output enable for Bank D outputs. See Table 3D for function. LVCMOS/LVTTL interface levels. 42 OEE Input Pullup Output enable for Bank E outputs. See Table 3E for function. LVCMOS/LVTTL interface levels. 43, 44 QC0, nQC0 Output Differential Bank C output pairs. LVPECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics NOTE: OEA is an asynchronous control. NOTE: OEB is an asynchronous control. NOTE: OEC is an asynchronous control. NOTE: OED is an asynchronous control. 45, 46 QC1, nQC1 Output Differential Bank C output pair. LVPECL interface levels. 47 V CCOC Power Output power supply for Bank C outputs. 48 OEF Input Pullup Output enable for Bank F outputs. See Table 3F for function. LVCMOS/LVTTL interface levels. 50, 63 V CCOF Power Output power supply for Bank F outputs. 51, 52 QF0, nQF0 Output Differential Bank F output pair. LVDS interface levels. 53, 54 QF1, nQF1 Output Differential Bank F output pair. LVDS interface levels. 55, 56 QF2, nQF2 Output Differential Bank F output pair. LVDS interface levels. 57, 58 QF3, nQF3 Output Differential Bank F output pair. LVDS interface levels. 59, 60 QF4, nQF4 Output Differential Bank F output pair. LVDS interface levels. 61, 62 QF5, nQF5 Output Differential Bank F output pair. LVDS interface levels. 0 Outputs QAx/nQAx are in a high-impedance state. 0 Outputs QBx/nQBx are in a high-impedance state. 0 Outputs QCx/nQCx are in a high-impedance state. 0 Outputs QDx/nQDx are in a high-impedance state.
4©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Table 3E. OEE Configuration Table NOTE: OEE is an asynchronous control Table 3F. OEF Configuration Table NOTE: OEF is an asynchronous control Table 3G. CLK_EN Mode Configuration Table NOTE: CLK_EN is synchronous to the falling edge of the input clock. Input OperationOEE 0 Outputs QEx/nQEx are in a high-impedance state. 1 Outputs are enabled. (Default) Input OperationOEF 0 Outputs QFx/nQFx are in a high-impedance state. 1 Outputs are enabled. (Default) Input OperationCLK_EN 0 Output clock signals are disabled (logic low). Stops the output clock signals in a logic low state, and thus, eliminates potential output runt pulses. 1 Output clock signals are enabled. (Default)
5©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = VCCOA = VCCOB = VCCOC = VCCODE = VCCOF = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C VCCOX denotes VCCOA, VCCOB, VCCOC, VCCODE, VCCOF.. ICCOX denotes ICCODE, ICCOF.. Table 4B. LVCMOS/LVTTL Input DC Characteristics, VCC = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, IO (LVDS) Continuous Current Surge Current 50mA 100mA 10mA 15mA Input Current, CLK, nCLK ±50mA V T Current, IVT ±100mA Input Sink/Source, IREF_AC ±2mA Package Thermal Impedance, JA 31.8°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 2.5 2.625 V VCCOX Output Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current No Load 47 54 mA ICCOX Output Supply Current No Load 139 160 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_EN OEA, OEB, OEC, OED, OEE, OEF VCC = VIN = 2.625V 5 µA IIL Input Low Current CLK_EN OEA, OEB, OEC, OED, OEE, OEF VCC = 2.625V, VIN = 0V -150 µA
6©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Table 4D. Differential LVPECL Input DC Characteristics, VCC = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Guaranteed by design. Table 4E. LVPECL DC Characteristics, VCC = VCCOA = VCCOB = VCCOC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VCCO – 2V. Table 4F. LVDS DC Characteristics, VCC = VCCODE = VCCOF = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units RIN Differential Input Resistance CLK, nCLK CLK-to-VT, nCLK-to-VT 40 50 60 VIH Input High Voltage CLK, nCLK 1.2 V CC V VIL Input Low Voltage CLK, nCLK 0 V IH – 0.15 V VIN Input Voltage Swing; NOTE 1 0.15 1.2 V VDIFF_IN Differential Input Voltage Swing 0.3 V IIN_CLK Input Current; NOTE 2 CLK, nCLK 35 mA VREF_AC Reference Voltage V CC – 1.4 V CC – 1.0 V CC – 0.80 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 V CCO – 1.4 V CCO – 0.8 V VOL Output Low Voltage; NOTE 1 V CCO – 2.0 V CCO – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.1 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 240 380 520 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.00 1.35 1.70 V VOS VOS Magnitude Change 50 mV
Table 5. AC Electrical Characteristics, VCC = VCCOA = VCCOB = VCCOC = = VCCODE = VCCOF = 2.5V ± 5%, VEE = 0V, has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
8©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator. Additive Phase Jitter @ 614.4MHz 10Hz to 10MHz = 0.05ps (typical) SSB Phase Noise dBc/Hz Offset from Carr ier Frequency (Hz)
9©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Parameter Measurement Information LVPECL Output Load AC Test Circuit Differential Input Level Output Skew LVDS Output Load AC Test Circuit Part-to-Part Skew Bank Skew SCOPE Qx nQx VEE -0.5V ± 0.125V VCC, VCCOA, VCCOB, VCCOC nCLK CLK VCC VEE VIH Cross Points V IN VIL nQx Qx nQy Qy VCC, VCCODE, VCCOF tsk(pp) VDDOX VDDOX Part 1 Part 2 Qx Qy nQXx QXx nQXx QXx tsk(b) Where X = Bank A, B, C, D, E or F
10©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet Parameter Measurement Information, continued LVPECL Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Offset Voltage Setup LVDS Output Rise/Fall Time Propagation Delay Differential Output Voltage Setup QA[0:2], QB[0:2], QC[0:1] nQA[0:2], nQB[0:2], nQC[0:1] QA[0:2], QB[0:2], QC[0:1], QD[0:2], QE[0:2], QF[0:5] nQA[0:2], nQB[0:2], nQC[0:1], nQD[0:2], nQE[0:2], nQF[0:5] 20% 80% 80% 20% tR tF VOD QD[0:2], QE[0:2], QF[0:5] nQD[0:2], nQE[0:2], nQF[0:5] tPD nQAx, nQBx, nQCx, nQDx, nQEx, nQFx QAx, QBx, QCx, QDx, QEx, QFx nCLK CLK
11©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet
Application Information
Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs All unused LVDS outputs should be terminated with 100 resistor between the differential pair.
This section provides information on power dissipation and junction temperature for the 874328I-01. Equations and example calculations are also provided. The total power dissipation for the 874328I-01 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VCC = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 31.8°C/W per Table 6 below. Table 6. Thermal Resistance JA for 64 Lead TQFP, E-Pad, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 6. Figure 6. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
This section provides information on power dissipation and junction temperature for the 874328I-01. Equations and example calculations are also provided. The total power dissipation for the 874328I-01 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VCC = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 31.8°C/W per Table 7 below. Table 7. Thermal Resistance JA for 64 Lead TQFP, E-Pad, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 8. JA vs. Air Flow Table for a 64 Lead TQFP, E-Pad
Table 9. Package Dimensions for 64 Lead TQFP, E-Pad
Table 10. Ordering Information
22©2016 Integrated Device Technology, Inc Revision A January 27, 2016 874328I-01 Data Sheet
Revision History
Revision Date Description of Change January 27, 2016 ▪ Removed ICS from part numbers where needed. ▪ General Description - Deleted ICS chip. ▪ Ordering Information - Deleted quantity from tape and reel. Deleted LF note below table. ▪ Updated header and footer.
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