87421 RENESAS | Alldatasheet
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÷1/÷2 Differential-to-LVDS Clock Generator 87421 Data Sheet ©2016 Integrated Device Technology, Inc June 24, 20161 GENERAL DESCRIPTION The 87421I is a high performance ÷1/÷2 Differential-to-LVDS Clock Generator. The CLK, nCLK pair can accept most standard differential input levels. The 87421I is characterized to operate from a 3.3V power supply. Guaranteed part-to-part skew characteristics make the 87421I ideal for those clock distribution applications demanding well defi ned performance and repeatability.
FEATURES
One differential LVDS output One differential CLK, nCLK input pair CLK, nCLK pair can accept the following differential input lev- els: LVPECL, LVDS, LVHSTL, SSTL, HCSL Maximum clock input frequency: 1GHz Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS levels with resistor bias on nCLK input Part-to-part skew: 500ps (maximum) Propagation delay: 1.7ns (maximum) Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical) Full 3.3V operating supply -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package For functional replacement device use 87321 BLOCK DIAGRAM P IN ASSIGNMENT 87421I 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View CLK nCLK MR F_SEL VDD Q nQ GND Q nQ CLK nCLK MR F_SEL ÷2R PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
87421 Data Sheet
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS TABLE 3. FUNCTION TABLE 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
enabled. LVCMOS / LVTTL interface levels. See Table 3. 4 F_SEL Input Pulldown Selects divider value for Q, nQ outputs as described in Table 3. LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. 6, 7 Q, nQ Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
1 X Reset: Q output low, nQ output high
©2016 Integrated Device Technology, Inc June 24, 20163 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V DD TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V DD ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, I O Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θ JA 96°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 55 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.37 V DD + 0.3 V V IL Input Low Voltage -0.3 0.7 V I IH Input High Current MR, F_SEL V DD = V IN = 3.465V 150 µA I IL Input Low Current MR, F_SEL V DD = 3.465V, V IN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current CLK V DD = V IN = 3.465V 150 µA nCLK V DD = V IN = 3.465V 5 µA I IL Input Low Current CLK V DD = 3.465V, V IN = 0V -5 µA nCLK V DD = 3.465V, V IN = 0V -150 µA V PP Peak-to-Peak Input Voltage 0.15 1.3 V V CMR Common Mode Input Voltage; NOTE 1 GND + 0.5 V DD - 0.85 V NOTE 1: Common mode voltage is defi ned as V IH
TABLE 5. AC CHARACTERISTICS, V NOTE 1: Measured from the differential input crossing point to the differential output crossing point. at the differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc June 24, 20165 ADDITIVE PHASE JITTER The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. of the device. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.17ps typical
©2016 Integrated Device Technology, Inc June 24, 20166 PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL OUTPUT VOLTAGE SETUP OFFSET VOLTAGE SETUP
©2016 Integrated Device Technology, Inc June 24, 20167
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT protection. A 1kΩ resistor can be used.
©2016 Integrated Device Technology, Inc June 24, 20168 FIGURE 3C. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY A 3.3V LVPECL DRIVER FIGURE 3B. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY A 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. FIGURE 3A. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY AN IDT OPEN EMITTER H IPERCLOCKS LVHSTL DRIVER Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK FIGURE 3E. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY A 3.3V HCSL DRIVER Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V FIGURE 3F. H IPERCLOCKS CLK/nCLK INPUT D RIVEN BY A 2.5V SSTL DRIVER
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION recommended to terminate the unused outputs.
This section provides information on power dissipation and junction temperature for the 87421I. Equations and example calculations are also provided. The total power dissipation for the 87421I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 5% = 3.465V, which gives worst case results. and a multi-layer board, the appropriate value is 96°C/W per Table 6 below. type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
TABLE 7. θ
TABLE 8. PACKAGE DIMENSIONS
TABLE 9. ORDERING INFORMATION
©2016 Integrated Device Technology, Inc June 24, 201614 REVISION HISTORY SHEET Rev Table Page Description of Change Date Updated data sheet format. 7/20/15 A T9 13 Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Ordering Information - Deleted LF note below table. Updated header and footer. 6/24/16
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