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Technical content

Features

  • One differential input reference clock
  • Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
  • Integrated input termination resistors
  • Eight LVDS outputs
  • Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
  • Maximum input clock frequency: 500MHz
  • LVCMOS interface levels for the control inputs
  • Internal regulator for improved noise immunity
  • Individual output enable/disabled by I2C interface
  • Output skew: 28ps
  • Additive Phase Jitter, RMS: 0.168ps (typical), 125MHz
  • Low additive phase jitter
  • Full 2.5V supply voltage
  • Available in Lead-free (RoHS 6) package
  • -40°C to 85°C ambient operating temperature Pin Assignment fREF IN nIN VT FSEL[1:0] SDA SCL ADR[1:0] Pullup Pullup Pulldown (2) nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 50 50 ÷1, ÷2, ÷4, ÷8 I2C Pulldown (2) 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ADR1 GND nQ0 nQ1 GND VDDO FSEL0 GND nQ7 nQ6 GND VDDO nQ2 nQ3 nQ4 nQ5 SCL SDA VDD nIN VT IN FSEL1 ADR0 ICS874208I

32 Lead VFQFN

5mm x 5mm x 0.925mm package body K Package Top View

REVISION A 9/18/14 2 ©2014 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics ADR0 Input Pulldown I2C Address inputs. LVCMOS/LVTTL compatible interface levels. 2, 7, 18, 23 GND Power Power supply ground. 3, 4 Q0, nQ0 Output Differential output pair 0. LVDS interface levels. 5, 6 Q1, nQ1 Output Differential output pair 1. LVDS interface levels. 8, 17 V DDO Power Output power supply pins. 9, 10 Q2, nQ2 Output Differential output pair 2. LVDS interface levels. 11, 12 Q3, nQ3 Output Differential output pair 3. LVDS interface levels. 13, 14 Q4, nQ4 Output Differential output pair 4. LVDS interface levels. 15, 16 Q5, nQ5 Output Differential output pair 5. LVDS interface levels. 19, 20 Q6, nQ6 Output Differential output pair 6. LVDS interface levels. 21, 22 Q7, nQ7 Output Differential output pair 7. LVDS interface levels. FSEL1 Input Pulldown Frequency divider select controls. See Table 3A for function. LVCMOS/LVTTL interface levels. 26 IN Input Non-inverting differential clock input.

27 V T

this pin. See input termination information in the applications section. 28 nIN Input Inverting differential clock input. 29 V DD Power Power supply pins. 30 SDA I/O Pullup I2C Data Input/Output. Input: LVCMOS/LVTTL interface levels. 31 SCL Input Pullup I2C clock input. LVCMOS/LVTTL compatible interface levels.

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 4 ©2014 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. NOTE 1: According to JEDEC/JESD 22-A114/22-C101. ESD ratings are target specifications. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDO = 2.5V, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.5V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, JA 33.1°C/W (0 mps) Storage Temperature, TSTG -65C to 150C Maximum Junction Temperature, TJMAX 125°C ESD - Human Body Model; NOTE 1 2000V ESD - Charged Device Model; NOTE 1 500V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units V DD Power Supply Voltage 2.375 2.5V 2.625 V VDDO Output Supply Voltage 2.375 2.5V 2.625 V IDD Power Supply Current 15 mA IDDO Output Supply Current 203 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 1.7 V DD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current FSEL1, FSEL0, ADR[1:0] V DD = VIN = 2.625V 150 µA SCK, SDA V DD = VIN = 2.625V 5 µA IIL Input Low Current FSEL1, FSEL0, ADR[1:0] V DD = 2.625V, VIN = 0V -5 µA SCK, SDA V DD = 2.625V, VIN = 0V -150 µA VIN Input Voltage Swing IN, nIN 0.15 1.2 V VCMR Common Mode Input Voltage; NOTE 1 1.2 V DD V VDIFF Differential Input Voltage Swing IN, nIN 0.3 2.4 V RIN Input Resistance IN, nIN to V T 45 50 66  RIN, DIFF Differential Input Resistance IN to nIN, VT = open 90 100 132 

REVISION A 9/18/14 5 ©2014 Integrated Device Technology, Inc. Table 5. AC Electrical Characteristics, VDD = VDDO = 2.5V, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 6 ©2014 Integrated Device Technology, Inc. Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter (100MHz) Measured using a Rohde & Schwarz SMA100 as the input source. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @ 100MHz 1MHz to 20MHz = 0.214ps (typical)

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 7 ©2014 Integrated Device Technology, Inc. Additive Phase Jitter (125MHz) Measured using a Rohde & Schwarz SMA100 as the input source. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @ 125MHz 1MHz to 20MHz = 0.168ps (typical)

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 8 ©2014 Integrated Device Technology, Inc. Additive Phase Jitter (156.25MHz) Measured using a Rohde & Schwarz SMA100 as the input source. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @ 156.25MHz 1MHz to 20MHz = 0.124ps (typical)

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 9 ©2014 Integrated Device Technology, Inc. Parameter Measurement Information LVDS Output Load AC Test Circuit Part-to-Part Skew Pulse Skew Differential Input Level Output Skew Output Rise/Fall Time VDD, VDDO nQx Qx nQy Qy tsk(pp) Part 1 Part 2 tPLH tPHL tsk(p) = |tPHL - tPLH| Qx nQx Qy nQy nIN IN VDD GND Cross Points VIN VCMR Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD Qx nQx

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 10 ©2014 Integrated Device Technology, Inc. Parameter Measurement Information, continued Propagation Delay Single-Ended & Differential Input Voltage Swing Offset Voltage Setup Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup nQx Qx nCLK CLK tPD VIN VDIFF_IN Differential Voltage Swing = 2 x Single-ended VIN Qx nQx

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 12 ©2014 Integrated Device Technology, Inc. VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 5: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. SOLDERSOLDER PINPIN EXPOSED HEAT SLUG PIN PAD PIN PADGROUND PLANE LAND PATTERN (GROUND PAD)THERMAL VIA

REVISION A 9/18/14 14 ©2014 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS874208I. Equations and example calculations are also provided. The total power dissipation for the ICS874208I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 33.1°C/W per Table 6 below. Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection

REVISION A 9/18/14 15 ©2014 Integrated Device Technology, Inc. Table 7. JA vs. Air Flow Table for a 32-Lead VFQFN

REVISION A 9/18/14 16 ©2014 Integrated Device Technology, Inc. Table 8. Package Dimensions package dimensions are in Table 8.

  1. Type A: Chamfer on the paddle (near pin 1)
  2. Type C: Mouse bite on the paddle (near pin 1)

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 17 ©2014 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information

874208I Data Sheet LVDS CLOCK DIVIDER AND FANOUT BUFFER REVISION A 9/18/14 18 ©2014 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date A 4B 4 Updated Minimum and Maximum levels of R IN and RIN, DIFF per PCN# N1408-01 9/18/14

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This produ ct is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright ©2014 Integrated Device Technology, Inc.. All rights reserved. Corporate Headquarters

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