ICS8741004I IDT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 20
Technical content
Features
- Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs
- One differential clock input pair
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Output frequency range: 98MHz - 160MHz
- Input frequency range: 98MHz - 128MHz
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 35ps (maximum)
- Full 3.3V operating supply
- Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
- -40°C to 85°C ambient operating temperature
- Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.925mm package body G Package Top View BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~600kHz (default) 1 = PLL Bandwidth: ~2MHz HiPerClockS™ ICS nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL nc VDDA F_SELA VDD OEA nQB1 QB1 VDDO QB0 nQB0 IREF F_SELB OEB GND GND nCLK CLK The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 2 ICS8741004BGI REV. B SEPTEMBER 27, 2007 Block Diagram F_SELA 0 ÷5 (default) 1 ÷4 F_SELB 0 ÷5 (default) 1 ÷4 VCO 490 - 640 MHz Phase Detector M = ÷5 (fixed) QA0 nQA0 QA1 nQA1 Pullup Pullup Pulldown Float Pulldown OEA OEB F_SELA F_SELB BW_SEL CLK nCLK MR IREF Pullup Pulldown Pulldown QB0 nQB0 QB1 nQB1 0 = ~200kHz Float = ~400kHz 1 = ~800kHz
Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 24 nQA1, QA1 Output Differential ou tput pair. LVDS interface levels. 3, 22 V DDO Power Output supply pins. 4, 5 QA0, nQA0 Output Differential outp ut pair. LVDS interface levels.
6 MR Input Pulldown
are enabled. LVCMOS/LVTTL interface levels.
7 BW_SEL Input Pullup/
Pulldown PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B. 9V DDA Power Analog supply pin. 10 F_SELA Input Pulldown Frequency select pins for QAx/nQAx outputs. LVCMOS/LVTTL interface levels. See Table 3C. 11 V DD Power Core supply pin.
12 OEA Input Pullup
Output enable for QAx pins. When HIGH, QAx/nQAx outputs are enabled. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 13 CLK Input Pulldown Non-inverting differential clock input. 14 nCLK Input Pullup Inverting differential clock input. 15, 16 GND Power Power supply ground.
17 OEB Input Pullup
Output enable for QBx pins. When HIGH, QBx/nQBx outputs are enabled. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 18 F_SELB Input Pulldown Frequency select pins for QBx/nQBx outputs. LVCMOS/LVTTL interface levels. See Table 3C.
19 IREF Input A fixed precision resistor (RREF = 475Ω) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs. 20, 21 nQB0, QB0 Output Differential ou tput pair. HCSL interface levels. 23, 24 QB1, nQB1 Output Differential ou tput pair. HCSL interface levels.
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 4 ICS8741004BGI REV. B SEPTEMBER 27, 2007 Function Tables Table 3A. Output Enable Function Table Table 3B. PLL Bandwidth Function Table Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Inputs Outputs OEA OEB QA[0:1]/nQA[0:1] QB[0:1]/nQB[0:1] 0 0 Hi-Z Hi-Z 1 1 Enabled Enabled Input PLL BandwidthBW_SEL 0 ~200kHz Float ~600kHz (default) 1~ 2 M H z Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 32.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 45 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 80 mA
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 5 ICS8741004BGI REV. B SEPTEMBER 27, 2007 Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage OEA, OEB, MR, F_SELA, F_SELB 2V DD + 0.3 V BW_SEL V DD – 0.3 V DD + 0.3 V VIL Input Low Voltage OEA, OEB, MR, F_SELA, F_SELB -0.3 0.8 V BW_SEL -0.3 +0.3 V VIM Input Mid Voltage BW_SEL V DD/2 – 0.1 V DD/2 + 0.1 V IIH Input High Current F_SELA, F_SELB, MR, BW_SEL VDD = VIN = 3.465V 150 µA OEA, OEB V DD = VIN = 3.465V 5 µA IIL Input Low Current MR, F_SELA, F_SELB, V DD = 3.465V, VIN = 0V -5 µA OEA, OEB, BW_SEL V DD = 3.465V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 GND + 0.5 V DD – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 290 390 490 mV ∆VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 1.35 1.5 V ∆VOS VOS Magnitude Change 50 mV
Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 7 ICS8741004BGI REV. B SEPTEMBER 27, 2007 Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Differential Input Level Cycle-to-Cycle Jitter 3.3V LVDS Output Load AC Test Circuit Bank Skew Output Duty Cycle/Pulse Width/Period RREF = 475Ω Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF VDDA VDD, VDDO nCLK CLK VDD GND VOS Cross Points V OD ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
nQA[0:1], nQB[0:1] QA[0:1], QB[0:1] SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDDA VDD, VDDO tsk(b) nQX0 QX0 nQX1 QX1 Where X is either Bank A or Bank B tPW tPERIOD tPW tPERIOD odc = x 100% nQA[0:1], nQB[0:1] QA[0:1], QB[0:1]
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 8 ICS8741004BGI REV. B SEPTEMBER 27, 2007 Parameter Measurement Information, continued HCSL Output Rise/Fall Time Differential Output Voltage Setup LVDS Output Rise/Fall Time Offset Voltage Setup Clock Outputs 0.175V 0.525V 0.525V 0.175V tR tF VSWING 100 out out LVDSDC Input VOD/∆ VOD VDD Clock Outputs 20% 80% 80% 20% tR tF VOD out out LVDSDC Input ➤ VOS/∆ VOS VDD
protection. A 1kΩ resistor can be used. pair should either be left floating or terminated. recommend that there is no trace attached. matched load termination of 100Ω across near the receiver input. it is recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination
Figure 6. P.C. Board for Exposed Pad Thermal Release Path Example
This section provides information on power dissipation and junction temperature for the ICS8741004I. Equations and example calculations are also provided. The total power dissipation for the ICS741004I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 32.1°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 24 Lead TSSOP, E-Pad, Forced Convection
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. Figure 8. LVHSTL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. θJA vs. Air Flow Table for a 24 Lead TSSOP, E-Pad
Table 9. Package Dimensions
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITT ER ATTENUATOR PRELIMINARY IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 19 ICS8741004BGI REV. B SEPTEMBER 27, 2007
Ordering Information
Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.
www.IDT.com © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Corporate Headquarters Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com ICS871004I DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JI TTER ATTENUATOR PRELIMINARY