ICS874005-04 IDT | Alldatasheet
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PCI EXPRESS™ JITTER ATTENUATOR ICS874005-04 IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 1 ICS874005AG-04 REV. A JULY 29, 2008 GENERAL DESCRIPTION The ICS874005-04 is a high performance Diff- erential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874005-04 has 2 PLL bandwidth modes: 300kHz and 2MHz. The 300kHz mode will provide maximum jitter attenuation, but higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles. The ICS874005-04 supports Serdes reference clock frequencies of 100MHz, 125MHz and 250MHz. The ICS874005-04 uses IDT’s 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.
FEATURES
- Five differential LVDS output pairs
- One differential clock input
- Supports 100MHz, 125MHz, and 250MHz Serdes reference clocks
- CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- Output frequency range: 98MHz - 320MHz
- Input frequency range: 98MHz - 128MHz PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
- RMS phase jitter @ 100MHz (1.875MHz – 20MHz): 0.88ps (typical)
- VCO range: 490MHz - 640MHz
- Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
- 3.3V operating supply
- Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package HiPerClockS™ ICS QA0 nQA0 BLOCK DIAGRAM BW_SEL 0 = PLL Bandwidth: ~300kHz (default) 1 = PLL Bandwidth: ~2MHz PLL BANDWIDTH F_SELA 0 ÷5 (default) 1 ÷4 F_SELB 0 ÷2 (default) 1 ÷4 VCO 490 - 640MHz Phase Detector M = ÷5 (fixed) Pulldown OEA F_SELA BW_SEL CLK nCLK F_SELB MR OEB Pullup QA1 nQA1 QB0 nQB0 QB1 nQB1 Pulldown Pulldown Pullup Pullup Pulldown PIN ASSIGNMENT ICS874005-04 24-Lead TSSOP 4.40mm x 7.8mm x 0.925mm package body G Package Top View nQB2 nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL VDDA F_SELA VDD OEA QB2 V DDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK Pulldown QB2 nQB2 0 = ~300kHz 1 = ~2MHz
TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 3 ICS874005AG-04 REV. A JULY 29, 2008 ICS874005-04 PCI EXPRESS™ JITTER ATTENUATOR TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH CONTROL, fREF = 100MHZ stupnI htdiwdnaBLLPLES_WB 0) tluafed(zHk003~ 1z HM2~ TABLE 3C. OUTPUT FREQUENCY FOR INPUT FREQUENCY = 100MHZ stupnIs tuptuO ALES_FB LES_Fx AQn/xAQx BQn/xBQ )tluafed(0) tluafed(0z HM001,5/OCVz HM052,2/OCV 01 z HM001,5/OCVz HM521,4/OCV 10 z HM521,4/OCVz HM052,2/OCV 11 z HM521,4/OCVz HM521,4/OCV stupnIs tuptuO BEO/AEOx AQn/xAQx BQn/xBQ 0e cnadepmIhgiHe cnadepmIhgiH 1d elbanEd elbanE ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 82.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 531.33 .35 64.3V V ADD egatloVylppuSgolanAV DD 01.0–3 .3V DD V V ODD egatloVylppuStuptuO 531.33 .35 64.3V I DD tnerruCylppuSrewoP 08A m I ADD tnerruCylppuSgolanA 01A m I ODD tnerruCylppuStuptuO 57A m
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C VsadenifedsiegatlovedomnommoC:2ETON HI .
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 5 ICS874005AG-04 REV. A JULY 29, 2008 ICS874005-04 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION CYCLE-TO-CYCLE JITTER DIFFERENTIAL INPUT LEVEL3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW VCMR Cross Points VPP GND CLK nCLK VDD tPW tPERIOD tPW tPERIOD odc = x 100% ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
QA0, QA1 QB0:QB2 nQA0, nQA1 nQB0:nQB2 SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODBANK SKEW t sk(o) nQy Qy nQx Qx QA0, QA1 QB0:QB2 nQA0, nQA1 nQB0:nQB2 VDD, VDDO VDDA t sk(b) nQy Qy nQx Qx
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 6 ICS874005AG-04 REV. A JULY 29, 2008 ICS874005-04 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED 20% 80% 80% 20% tR tF VOD DIFFERENTIAL OUTPUT VOL TAGE SETUP OUTPUT RISE/FALL TIME 100 out out LVDSDC Input VOD/Δ VOD VDD out out LVDSDC Input ➤ VOS/Δ VOS VDD OFFSET VOLTAGE SETUP QA0, QA1 QB0:QB2 nQA0, nQA1 nQB0:nQB2
FIGURE 5. ICS874005-04 SCHEMATIC EXAMPLE
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION to the power pin. The input is driven by a 3.3V LVPECL driver.
This section provides information on power dissipation and junction temperature for the ICS874005-04. Equations and example calculations are also provided.
- Power Dissipation (typical).
= 3.3V + 5% = 3.465V, which gives worst case results.
- Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX ) = 3.465V * (80mA + 10mA) = 311.85mW
- Power (outputs) MAX = V DDO_MAX * I DDO_MAX = 3.465V * 75mA = 259.875mW Total Power _MAX = 311.85mW + 259.875mW = 571.725mW 2. Junction T emperature (typical). Junction temperature, Tj, is the t emperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = T otal Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board.
TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 24-LEAD TSSOP, FORCED CONVECTION
TABLE 7. θ
TABLE 9. ORDERING INFORMATION
PCI EXPRESS™ JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA