ICS874003-05 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Three differential LVDS output pairs
  • One differential clock input
  • CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Input frequency range: 98MHz to 128MHz
  • Output frequency range: 98MHz to 320MHz
  • VCO range: 490MHz - 640MHz
  • Supports PCI-Express Spread-Spectrum Clocking
  • High PLL bandwidth allows for better input tracking
  • PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
  • 0°C to 70°C ambient operating temperature
  • Full 3.3V operating supply
  • Available in lead-free (RoHS 6) packages F_SEL[2:0] Function Table HiPerClockS™ ICS Inputs Outputs F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0 0 (default) 0 (default) 0 (default) ÷2 ÷2 100 ÷ 5 ÷ 2 010 ÷ 4 ÷ 2 110 ÷ 2 ÷ 4 001 ÷ 2 ÷ 5 101 ÷ 5 ÷ 4 011 ÷ 4 ÷ 5 111 ÷ 4 ÷ 4 F_SEL1 VDDA nc F_SEL0 MR nQA0 QA0 VDDO QA1 VDD nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA Pin Assignment ICS874003-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 2 ICS874003BG-05 REV. A APRIL 15, 2009 Block Diagram (default) (default) VCO 490 - 640MHz Phase Detector M = ÷5 (fixed) QA0 nQA0 QA1 nQA1 QB0 nQB0 Pullup Pulldown Pulldown Pullup Pulldown Pullup OEA F_SEL2:0 CLK nCLK MR OEB

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Output Enable Function Table 1, 20 QA1, nQA1 Output Bank A differential output pair. LVDS interface levels. 2, 19 V DDO Power Output supply pins. 3, 4 QA0, nQA0 Output Bank A differential output pair. LVDS interface levels.

5 MR Input Pulldown

high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Input Pulldown Frequency select pin for QAx/nQAx and QB0/nQB0 outputs. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 10 V DD Power Core supply pin.

11 OEA Input Pullup

Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground.

15 OEB Input Pullup

Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active. When LOW, the QB0/nQB0 outputs are in a high-impedance state. LVCMOS/LVTTL interface levels. 17, 18 nQB0, QB0 Output Bank B differential output pair. LVDS interface levels.

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 4 ICS874003BG-05 REV. A APRIL 15, 2009 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics,VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.16 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 75 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OEA, OEB V DD = VIN = 3.465V 5 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB V DD = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL1, F_SEL2, MR V DD = 3.465V, VIN = 0V -5 µA

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 5 ICS874003BG-05 REV. A APRIL 15, 2009 Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK V DD = 3.465V, VIN = 0V -5 µA nCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VOD Differential Output Voltage 275 375 485 mV ∆VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.20 1.35 1.50 V ∆VOS VOS Magnitude Change 50 mV

Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C thermal equilibrium has been reached under these conditions. composite transfer function. NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 7 ICS874003BG-05 REV. A APRIL 15, 2009 Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Bank Skew Output Skew Differential Input Level Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND LVDS VDDA VDD, VDDO tsk(b) QA0 nQA0 QA1 nQA1 tsk(o) Qx nQx Qy nQy VDD nCLK CLK GND VCMR Cross Points VPP ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QAx, QB0 nQAx, nQB0 tPW tPERIOD tPW tPERIOD odc = x 100% QAx, QB0 nQAx, nQB0

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 8 ICS874003BG-05 REV. A APRIL 15, 2009 Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Setup Offset Voltage Setup 20% 80% 80% 20% tR tF VOD QAx, QB0 nQAx, nQB0 100 out out LVDSDC Input VOD/∆ VOD VDD out out LVDSDC Input ➤ VOS/∆ VOS VDD

protection. A 1kΩ resistor can be used. matched load termination of 100Ω across near the receiver input. it is recommended to terminate the unused outputs. Figure 4. Typical LVDS Driver Termination

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 13 ICS874003BG-05 REV. A APRIL 15, 2009 PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as well as the overall transfer function Ht. The respective -3 dB pole frequencies for each transfer function are labeled as F1 for transfer function H1, F2 for H2, and F3 for H3. For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. Ht s() H3 s() H1 s() H2 s()–[]×= Ys() Xs() H3 s()× H1 s() H2 s()–[]×=

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 14 ICS874003BG-05 REV. A APRIL 15, 2009 PCIe Gen 1 Magnitude of Transfer Function PCIe Gen 2A Magnitude of Transfer Function PCIe Gen 2B Magnitude of Transfer Function -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 1 F1: 2.2e+007 F2: 1.5e+006 F3: 1.5e+006 Ht=(H1-H2)*H3 -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 2A F1: 1.6e+007 F2: 5.0e+006 F3: 1.0e+006 Ht=(H1-H2)*H3 -60 -50 -40 -30 -20 -10 Frequency (Hz) Mag (dB) Magnitude of Transfer Functions - PCIe Gen 2B F1: 1.6e+007 F2: 8.0e+006 F3: 1.0e+006 Ht=(H1-H2)*H3

This section provides information on power dissipation and junction temperature for the ICS874003-05. Equations and example calculations are also provided. load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

PCI EXPRESS™ JITTER ATTENUATOR IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 17 ICS874003BG-05 REV. A APRIL 15, 2009

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT product for use in life support devices or critical medical instruments.

PCI EXPRESS™ JITTER ATTENUATOR www.IDT.com © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

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