ICS874003-02_10 IDT | Alldatasheet

Document overview

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Technical content

Features

  • Three differential LVDS output pairs
  • One differential clock input
  • CLK, nCLK supports the following input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
  • Input frequency range: 98MHz to 128MHz
  • Output frequency range: 98MHz to 320MHz
  • VCO range: 490MHz - 640MHz
  • Cycle-to-cycle jitter: 35ps (maximum)
  • For PCI Express Spread Spectrum Clocking support use the ICS874003-05
  • Full 3.3V supply mode
  • 0°C to 70°C ambient operating temperature
  • Available in both standard (RoHS 5) and lead-free (RoHS 6) packagesF_SEL[2:0] Function Table Inputs Outputs F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0 000 ÷ 2 ÷ 2 100 ÷ 5 ÷ 2 010 ÷ 4 ÷ 2 110 ÷ 2 ÷ 4 001 ÷ 2 ÷ 5 101 ÷ 5 ÷ 4 011 ÷ 4 ÷ 5 111 ÷ 4 ÷ 4 F_SEL1 VDDA nc F_SEL0 MR nQA0 QA0 VDDO QA1 VDD nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA Pin Assignment ICS874003-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 2 ©2010 Integrated Device Technology, Inc. Block Diagram (default) (default) VCO 490 - 640MHz Phase Detector M = ÷5 (fixed) QA0 nQA0 QA1 nQA1 QB0 nQB0 Pullup Pulldown Pulldown Pullup Pulldown Pullup OEA F_SEL2:0 CLK nCLK MR OEB

ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 3 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Table 3. Output Enable Function Table 1, 20 QA1, nQA1 Output Differential ou tput pair. LVDS interface levels. 2, 19 V DDO Power Output supply pins. 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels.

5 MR Input Pulldown

causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. DDA Power Analog supply pin. 10 V DD Power Core supply pin.

11 OEA Input Pullup

Output enable pin for QA pins. When HIGH, the QAx, nQAx outputs are active. When LOW, the QAx, nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground.

15 OEB Input Pullup

Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active. When LOW, the QB0, nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 17, 18 nQB0, QB0 Output Differential ou tput pair. LVDS interface levels.

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 4 ©2010 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 75 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OEA, OEB V DD = VIN = 3.465V 5 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB V DD = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL1, F_SEL2, MR V DD = 3.465V, VIN = 0V -5 µA

ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 5 ©2010 Integrated Device Technology, Inc. NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 5. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 6 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Bank Skew Output Skew Differential Input Level Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period SCOPE Qx nQx 3.3V±5% POWER SUPPL Y +–Float GND VDDA VDD, VDDO tsk(b) QA0 nQA0 QA1 nQA1 tsk(o) Qx nQx Qy nQy VDD nCLK CLK GND VCMR Cross Points VPP ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

QA[0:1], QB0 nQA[0:1], nQB0 tPW tPERIOD tPW tPERIOD odc = x 100% QA[0:1], QB0 nQA[0:1], nQB0

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 7 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Setup Offset Voltage Setup 20% 80% 80% 20% tR tF VOD QA[0:1], QB0 nQA[0:1], nQB0 100 out out LVDSDC Input VOD/∆ VOD VDD out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 10 ©2010 Integrated Device Technology, Inc. Recommendations for Unused Input and Output Pins Inputs: LVCMOS Control Pins All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 4 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output.Figure 4. Typical LVDS Driver Termination 100Ω 100Ω Differential Transmission Line LVDS Driver LVDS Receiver

ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 11 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS874003-02. Equations and example calculations are also provided. The total power dissipation for the ICS74003-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 12 ©2010 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 13 ©2010 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 14 ©2010 Integrated Device Technology, Inc. Revision History Sheet Rev Table Page Description of Change Date B T4C 6 - 7 Updated General Description and Features section. Pin Description Table - corrected MR description Differential DC Characteristics Table - updated notes. Added Units to IIH/IIL rows. Corrected IIH (nCLK) spec from 5uA min to 5uA max. Corrected IIL CLK from 150uA max to -5uA min. AC Characteristics Table - added thermal note, corrected NOTE 2. Parameter Measurement Information - corrected Bank Skew labels, corrected Output Rise/Fall Time diagram. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated Differential Clock Input Interface. Updated LVDS Driver Termination. Ordering Information Table - deleted "ICS" prefix in Part/Order column, added "ICS" prefix to marking column. Converted datasheet format. 9/14/10

ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. Performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informati on contained herein is provided without re presentation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of IDT’s products for any particular purpose, an im plied warranty of merchantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

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