ICS874001I-05 IDT | Alldatasheet

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PCI EXPRESS™ JITTER ATTENUATOR ICS874001I-05 IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 1 ICS874001AGI-05 REV. A APRIL 20, 2009 GENERAL DESCRIPTION The ICS874001I-05 is a high performance Jitter Attenuator designed for use in PCI Express™ sys- tems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874001I-05 has a bandwidth of 6MHz with <1dB peaking, easily meeting PCI Express Gen2 PLL requirements. The ICS874001I-05 uses IDT’s 3 rd Generation FemtoClock TM PLL technology to achive the lowest possible phase noise. The device is packaged in a small 20-pin TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards.

FEATURES

  • One differential LVDS output pair
  • One differential clock input
  • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Output frequency range: 98MHz - 640MHz
  • Input frequency range: 98MHz - 128MHz
  • VCO range: 490MHz - 640MHz
  • Cycle-to-cycle jitter: 50ps (maximum)
  • 3.3V operating supply  PCI Express (2.5Gb/s) and Gen 2 (5 Gb/s) jitter compliant
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package HiPerClockS™ ICS PIN ASSIGNMENT PLL_SEL nc nc nc MR nc F_SEL1 VDDA F_SEL0 VDD nc V DDO Q nQ nc nc GND nCLK CLK OE ICS874001I-05 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 2 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR BLOCK DIAGRAM Phase Detector VCO 490 - 640MHz Output Divider 0 0 ÷5 0 1 ÷4 1 0 ÷2 (default) 1 1 ÷1 Internal Feedback Q nQ PLL_SEL CLK nCLK MR F_SEL[1:0] OE Pulldown Pullup/Pulldown Pullup Pullup Pullup Pulldown

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 4 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional op- eration of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V , TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 0.33 .36 .3V V ADD egatloVylppuSgolanAV DD 31.0–3 .3V DD V V ODD egatloVylppuStuptuO 0.33 .36 .3V I DD tnerruCylppuSrewoP 57A m I ADD tnerruCylppuSgolanA 31A m I ODD tnerruCylppuStuptuO 52A m TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V , TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI egatloVhgiHtupnI 2V DD 3.0+V V LI egatloVwoLtupnI 3.0-8 .0V I HI tupnI tnerruChgiH LES_LLP,EO,1LES_FV DD V= NI V6.3=5 A µ RM,0LES_FV DD V= NI V6.3=0 51A µ I LI tupnI tnerruCwoL LES_LLP,EO,1LES_F V DD =, V6.3V NI V0= 051-A µ RM,0LES_F V DD =, V6.3V NI V0= 5-A µ TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V , TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU I HI tnerruChgiHtupnI KLCV DD V= NI V6.3=0 51A µ KLCnV DD V= NI V6.3=5 A µ I LI tnerruCwoLtupnI KLCV DD V,V6.3= NI V0=5 -A µ KLCnV DD V,V6.3= NI V0=0 51-A µ V PP 1ETON;egatloVtupnIkaeP-ot-kaeP 51.03 .1V V RMC 2,1ETON;egatloVtupnIedoMnommoC 5.0+DNGV DD 58.0-V V:1ETON LI .V3.0-nahtsselebtsum VsadenifedsiegatlovedomnommoC:2ETON HI . TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V, TA = -40°C TO 85°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DO egatloVtuptuOlaitnereffiD 5725 735 84V m Δ V DO V DO egnahCedutingaM 05V m V SO egatloVtesffO 02.15 3.10 5.1V Δ V SO V SO egnahCedutingaM 05V m

TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 0.3V , TA = -40°C TO 85°C

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 6 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER V CMR Cross Points V PP GND CLK nCLK VDD tPW tPERIOD tPW tPERIOD odc = x 100% Q nQ Q nQ SCOPE Qx nQx 3.3V±0.3V POWER SUPPL Y +–Float GND LVDS OUTPUT RISE/FALL TIME VDD, VDDO VDDA 20% 80% 80% 20% tR tF VOD Q nQ DIFFERENTIAL INPUT LEVEL ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

DIFFERENTIAL OUTPUT VOLTAGE SETUP 100 out out LVDSDC Input VOD/Δ VOD VDD

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 7 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION, CONTINUED OFFSET VOLTAGE SETUP out out LVDSDC Input ➤ VOS/Δ VOS VDD

FIGURE 4. TYPICAL LVDS DRIVER TERMINATION protection. A 1k Ω resistor can be used.

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 12 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PCI EXPRESS APPLICATION NOTE PCI Express jitter analysis methodology models the system response to reference clock jitter. The below block diagram shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided ot both ends of the PCI Express Link. In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well as the phase interpolator in the receiver. These ransfer functions are called H1, H2 and H3 respectively. The overall system transfer function at the receiver is: Ht(s) = H3(s) * [H1(s) - H2(s)] The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y(s) = X(s) * H3(s) * [H1(s) - H2(s)] In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s) * H3(s) * [H1(s) - H2(s)]. For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is reported in peak-peak. For PCI Express Gen2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band). The below plots show the individual transfer functions as function H1, F2 for H2, and f# for H3. For a more thorough overivew of PCI Express jitter analysis methodology, please refer to IDT Application Note, PCI Express Reference Clock Requirements. Reference Clock Tx Serdes PLL x25 Mult H1(s)

100 MHz

X(s) 100 MHz X(s) PLL x25 Mult H2(s) Phase Aligner H3(s) QD Rx Serdes - Y(s) System Transfer Function, Ht(s) = H3(s) * [H1(s) - H2(s)] Reference Clock Spectrum seen by Receiver Sample Latch, Y(s) = X(s) * Ht(s)

2.5 GHz

IDT™ / ICS™ PCI EXPRESS JITTER ATTENUATOR 13 ICS874001AGI-05 REV. A APRIL 20, 2009 ICS874001I-05 PCI EXPRESS™ JITTER ATTENUATOR PCIe GEN 1 MAGNITUDE OF TRANSFER FUNCTION PCIe GEN 2A MAGNITUDE OF TRANSFER FUNCTION PCIe GEN 2B MAGNITUDE OF TRANSFER FUNCTION

This section provides information on power dissipation and junction temperature for the ICS874001I-05. Equations and example calculations are also provided. The total power dissipation for the ICS874001I-05 is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 0.3V = 3.6V, which gives worst case results.

  • Power (core) MAX = V DD_MAX * (I DD_MAX + I DDA_MAX
  • Power (outputs) MAX = V DDO_MAX * I DDO_MAX = 3.6V * 25mA = 90mW Total Power _MAX = 316.8mW + 90mW = 406.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board.

TABLE 6. THERMAL RESISTANCE θθθθθJA FOR 20-LEAD TSSOP, FORCED CONVECTION

TABLE 7. θ TABLE 8. PACKAGE DIMENSIONSPACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. TABLE 9. ORDERING INFORMATION

PCI EXPRESS™ JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contact IDT For Tech Support netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA