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Low Skew, ÷2/4,÷4/5/6, Differential-to-3.3V LVPECL Clock Generator 87339I-11 Data Sheet ©2016 Integrated Device Technology, Inc Revision B January 25, 20161 GENERAL DESCRIPTION The 87339I-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/Divider. The 87339I-11 has one differential clock input pair. The CLK, nCLK pair can accept most standard differential input levels. The clock enable isinternally synchronized to eliminate runt pulses on theoutputs during asynchronous as- sertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew charac- teristics make the 87339I-11 ideal for clock distribution applications demanding well defined performance and repeatability.

FEATURES

  • Dual ÷2, ÷4 differential 3.3V LVPECL outputs; Dual ÷4, ÷5, ÷6 differential 3.3V LVPECL outputs
  • One differential CLK, nCLK input pair
  • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
  • Maximum clock input frequency: 1GHz
  • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels with resistor bias on nCLK input
  • Output skew: 35ps (maximum)
  • Part-to-part skew: 385ps (maximum)
  • Bank skew: Bank A - 20ps (maximum) Bank B - 20ps (maximum)
  • Propagation delay: 2.1ns (maximum)
  • LVPECL mode operating voltage supply range: VCC = 3V to 3.6V, VEE = 0V
  • Available in lead-free (RoHS 6) package BLOCK DIAGRAM P IN ASSIGNMENT 87339I-11 20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body G Package Top View 20-Lead SOIC, 300MIL 7.5mm x 12.8mm x 2.25mm package body M Package Top View

TABLE 2. PIN CHARACTERISTICS TABLE 1. PIN DESCRIPTIONS 1, 8, 20 V CC Power Positive supply pins. 2 nCLK_EN Input Pulldown Clock enable. LVCMOS / LVTTL interface levels. See Table 3. 3 DIV_SELB0 Input Pulldown Selects divide value for Bank B outputs as described in Table 3. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 RESERVED Reserve Reserve pin.

7 MR Input Pulldown

high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. 9 DIV_SELB1 Input Pulldown Selects divide value for Bank B outputs as described in Table 3. LVCMOS / LVTTL interface levels. 10 DIV_SELA Input Pulldown Selects divide value for Bank A outputs as described in Table 3. LVCMOS / LVTTL interface levels. EE Power Negative supply pin. 12, 13 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 14, 15 nQB0, QB0 Output Differential output pair. LVPECL interface levels. 16, 17 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 18, 19 nQA0, QA0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 3. CONTROL INPUT FUNCTION TABLE

1 X X X X LOW HIGH LOW HIGH

01 X X X Not Switch-

NOTE: After nCLK_EN switches, the clock outputs stop switching following a rising and falling input clock edge.

©2016 Integrated Device Technology, Inc Revision B January 25, 20164 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 3.0 3.3 3.6 V IEE Power Supply Current 105 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V CC + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current nCLK_EN, MR, DIV_SELA, DIV_SELBx VIN = VCC = 3.6V 150 µA IIL Input Low Current nCLK_EN, MR, DIV_SELA, DIV_SELBx VIN = 0V, VCC = 3.6V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current nCLK V IN = VCC = 3.6V 5 µA CLK V IN = VCC = 3.6V 150 µA IIL Input Low Current nCLK V IN = 0V, VCC = 3.6V -150 µA CLK V IN = 0V, VCC = 3.6V -5 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 V CC - 0.85 V NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 20 Lead TSSOP 73.2°C/W (0 lfpm) 20 Lead SOIC 46.2°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±0.3V, TA = -40°C TO 85°C All data taken with outputs ÷4. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defi ned as skew within a bank of outputs and with equal load conditions. at the differential cross points. NOTE 5: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 1: Outputs terminated with 50Ω to VCC - 2V.

©2016 Integrated Device Technology, Inc Revision B January 25, 20166 PARAMETER MEASUREMENT INFORMATION PART-TO-PART SKEW BANK SKEW OUTPUT RISE/FALL TIME DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

©2016 Integrated Device Technology, Inc Revision B January 25, 20169 POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 87339I-11. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 87339I-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core)MAX = VCC_MAX * ICC_MAX = 3.6V * 105mA = 378mW
  • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 30mW = 120mW Total Power_MAX (3.6V, with all outputs switching) = 378mW + 120mW = 498mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) Table 6A. Thermal Resistance θJA for 20-pin TSSOP, Forced Convection θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 6B. Thermal Resistance θJA for 20-pin SOIC, Forced Convection
  1. Calculations and Equations.

LVPECL output driver circuit and termination are shown in Figure 5. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION

©2016 Integrated Device Technology, Inc Revision B January 25, 201611 RELIABILITY INFORMATION TRANSISTOR COUNT The transistor count for 87339I-11 is: 1745 Compatible with MC10EP139, MC100EP139 TABLE 7B. θJAVS. AIR FLOW SOIC TABLE θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 83.2°C/W 65.7°C/W 57.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards 46.2°C/W 39.7°C/W 36.8°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. θJA by Velocity (Linear Feet per Minute) TABLE 7A. θJAVS. AIR FLOW TSSOP TABLE

©2016 Integrated Device Technology, Inc Revision B January 25, 201612 PACKAGE OUTLINE - M SUFFIX FOR 20 LEAD SOIC TABLE 8B. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MS-013, MO-119 SYMBOL Millimeters Minimum Maximum N2 0 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 12.60 13.00 E 7.40 7.60 e 1.27 BASIC H 10.00 10.65 h 0.25 0.75 L 0.40 1.27 α 0° 8° PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8A. PACKAGE DIMENSIONS Reference Document: JEDEC Publication 95, MO-153 SYMBOL Millimeters MIN MAX N2 0 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 BASIC E1 4.30 4.50 e 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10

TABLE 9. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision B January 25, 201614 REVISION HISTORY SHEET Rev Table Page Description of Change Date AT 1 Pin Assignment - changed pin 6, “nc” to “reserved”. Pin Description table - corrected pin 6 to read reserved to coordinate with Pin Assignment. 3/10/05 A T9 Features section - corrected Output skew and Part-to-Part skew bullets. Ordering Information table - added Lead-Free note. 4/12/05 BT 9 1 3 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 8/2/10 BT 9 Remove ICS from part numbers where needed. Features section - removed reference to leaded package. Ordering Information - remove quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1/25/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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