87332I-01 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: rdvorak
  • PDF pages: 15

Technical content

÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator 87332I-01 DATA SHEET 87332AMI-01 REVISION C 2/12/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 87332I-01 is a high performance ÷2 Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept most standard differential input levels The 87332I-01 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 87332I-01 ideal for those clock distribution applications demanding well defi ned performance and repeatability.

FEATURES

 One ÷2 differential 2.5V/3.3V LVPECL / ECL output  One CLK, nCLK input pair  CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  Maximum output frequency: 500MHz  Maximum input frequency: 1GHz  Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input  Part-to-part skew: 400ps (maximum)  Propagation delay: 1.6ns (maximum)  LVPECL mode operating voltage supply range: V CC = 2.375V to 3.8V, VEE = 0V  ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.8V  -40°C to 85°C ambient operating temperature  Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 87332I-01 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View MR CLK nCLK nc Vcc Q nQ V EE Q nQ CLK nCLK ÷2 MR

2 REVISION C 2/12/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

1 MR Input Pulldown

divider is reset forcing Q output LOW and nQ output HIGH. LVCMOS / LVTTL interface level. 2 CLK Input Pulldown Non-inverting differential clock input. 3 nCLK Input Pullup Inverting differential clock input. EE Power Negative supply pin. 6, 7 Q, nQ Output Differential output pair. LVPECL interface levels. 8V CC Power Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. FIGURE 1. TIMING DIAGRAM

3 ÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 3.3 3.8 V IEE Power Supply Current 30 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V CC = VIN = 3.8V 150 µA nCLK VCC = VIN = 3.8V 5 µA IIL Input Low Current CLK V CC = 3.8V, VIN = 0V -5 µA nCLK VCC = 3.8V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 V NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage MR 2 VCC + 0.3 V VIL Input Low Voltage MR -0.3 0.8 V IIH Input High Current MR VCC = VIN = 3.8V 150 µA IIL Input Low Current MR VCC = 3.8V, VIN = 0V -5 µA TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to VCC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability.

4 REVISION C 2/12/15

TABLE 4. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C specifi cations after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. at the differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 1: Outputs terminated with 50Ω to VCC - 2V.

5 ÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator PARAMETER MEASUREMENT INFORMATION OUTPUT RISE/FALL TIME DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator 87332AMI-01 DATA SHEET

6 REVISION C 2/12/15

APPLICATION INFORMATION

Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT recommended only as guidelines. circuit and clock component process variations.

÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator 87332AMI-01 DATA SHEET

8 REVISION C 2/12/15

FIGURE 5C. CLK/nCLK I NPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 5B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 5D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V OH must meet the VPP and VCMR input requirements. Figures 5A to 5F show interface examples for the CLK/nCLK input driven by the most common driv- er types. The input interfaces suggested here are examples only. FIGURE 5A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER LVHSTL DRIVER Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 5A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK FIGURE 5E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V FIGURE 5F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER

This section provides information on power dissipation and junction temperature for the 87332I-01. Equations and example calculations are also provided. The total power dissipation for the 87332I-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW
  • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.8V, with all outputs switching) = 114mW + 30mW = 144mW 2. Junction Temperature. Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = J unction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.144W * 103.3°C/W = 99.9°C. This is well below the limit of 125°C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (multi-layer). θJA by Velocity (Linear Feet per Minute)

TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

10 REVISION C 2/12/15

  1. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 6. θJAVS. AIR FLOW TABLE NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TABLE 7. PACKAGE DIMENSIONS

12 REVISION C 2/12/15

TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

13 ÷2, Differential-to-2.5V/3.3V ECL/LVPECL Clock Generator REVISION HISTORY SHEET Rev Table Page Description of Change Date B Features Section - added Lead-Free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Added “Wiring the Differential Input to Accept Single Ended Levels. Added Termination for 3.3V LVPECL Output. Added Termination for 2.5V LVPECL Output. Added Differential Clock Input Interface. Ordering Information Table - corrected marking. Added Lead-Free part number and note. Updated format of datasheet. 7/5/05 C T3D 4 9 - 10 LVPECL DC Characteristics Table -corrected V OH max. from VCC - 1.0V to Power Considerations - corrected power dissipation to refl ect VOH max in Table 3D. 4/13/07 C T4 4 Added thermal note to AC Characteristics table. Updated fi gures 3A & 3B, LVPECL Output Termination diagrams. Updated Differential Clock Input Interface. Ordering Information Table - add LF marking. Deleted “ICS” prefi x from part/order num- ber. Updated header/footer of datasheet. 11/16/09

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.