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Technical content
Features
- Ten differential 3.3V LVPECL outputs
- Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs
- CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL
- CLK1 accepts the following input levels: LVCMOS or LVTTL
- Maximum output frequency: 350MHz
- VCO range: 250MHz to 700MHz
- External feedback for “zero delay” clock regeneration with confi gurable frequencies
- Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) CLK1, 80ps (maximum)
- Output skew: 150ps (maximum)
- Static phase offset: -150ps to 150ps
- Lead-Free package fully RoHS compliant BLOCK DIAGRAM P IN ASSIGNMENT 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View ICS8732-01 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO QA0 nQA1 VEE PLL_SEL VEE VCCO nQA2 QA3 nQA3 VCCO nQB3 QB2 VEE VEE MR VCCO QB1 nQB0 QB0 DIV_SELA1 DIV_SELB0 DIV_SELA0 VCC VEE CLK1 nCLK0 CLK0 CLK_SEL VCCA nc DIV_SELB1 VCC FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN FB_IN VCC VEE VCCO nQFB0 QFB0 nQFB1 QFB1 VEE 4849505152 47 46 45 44 43 42 41 40
TABLE 1. PIN DESCRIPTIONS 39, 40 VCCO Power Output supply pins. QA1, nQA1 Output Differential output pair. LVPECL interface levels. EE Power Negative supply pins.
7 PLL_SEL Input Pullup
Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. QA3, nQA3 Output Differential output pairs. LVPECL interface levels. 14 DIV_SELA1 Input Pulldown Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. 15 DIV_SELA0 Input Pulldown Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. 18 CLK1 Input Pulldown LVCMOS / LVTTL reference clock input. 19 nCLK0 Input Pullup Inverting differential clock input. 20 CLK0 Input Pulldown Non-inverting differential clock input. 21 CLK_SEL Input Pulldown Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. CCA Power Analog supply pin. 24 DIV_SELB1 Input Pulldown Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. 25 DIV_SELB0 Input Pulldown Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. QB1, nQB1 Output Differential output pairs. LVPECL interface levels.
33 MR Input Pulldown
abled. LVCMOS / LVTTL interface levels. QB3, nQB3 Output Differential output pairs. LVPECL interface levels. QFB0, nQFB0 Output Differential feedback output pairs. LVPECL interface levels.
47 FB_IN Input Pulldown Feedback input to phase detector for regenerating clocks
49 FBDIV_SEL0 Input Pulldown Selects divide value for differential feedback output pairs. LVCMOS / LVTTL interface levels. 50 FBDIV_SEL1 Input Pulldown Selects divide value for differential feedback output pairs. LVCMOS / LVTTL interface levels. 51 FBDIV_SEL2 Input Pulldown Selects divide value for differential feedback output pairs. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
1 X X X Low
©2016 Integrated Device Technology, Inc Revision E January 22, 20164 TABLE 4A. QX OUTPUT FREQUENCY W/FB_IN = QFB0 OR QFB1 Inputs fVCO FB_IN FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 Output Divider Mode CLK1 (MHz) (NOTE 1)Minimum Maximum QFB 0 0 0 ÷4 62.5 175 (NOTE 2) fREF_CLK x 4 QFB 0 0 1 ÷6 41.67 116.67 fREF_CLK x 6 QFB 0 1 0 ÷8 31.25 87.5 fREF_CLK x 8 QFB 0 1 1 ÷10 25 70 fREF_CLK x 10 QFB 1 0 0 ÷8 31.25 87.5 fREF_CLK x 8 QFB 1 0 1 ÷12 20.83 58.33 fREF_CLK x 12 QFB 1 1 0 ÷16 15.62 43.75 fREF_CLK x 16 QFB 1 1 1 ÷20 12.5 35 fREF_CLK x 20 NOTE 1: VCO frequency range is 250MHz to 700MHz. NOTE 2: The maximum input frequency that the phase detector can accept is 175MHz. TABLE 3C. CONTROL INPUT FUNCTION TABLE FOR QFB0, QFB1 Inputs Outputs MR PLL_SEL FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 QFB0, QFB1 nQFB0, nQFB1 1X X X X L o w 0 1 0 0 0 fVCO/4 0 1 0 0 1 fVCO/6 0 1 0 1 0 fVCO/8 0 1 0 1 1 fVCO/10 0 1 1 0 0 fVCO/8 0 1 1 0 1 fVCO/12 0 1 1 1 0 fVCO/16 0 1 1 1 1 fVCO/20 0 0 0 0 0 fREF_CLK/4 0 0 0 0 1 fREF_CLK/6 0 0 0 1 0 fREF_CLK/8 0 0 0 1 1 fREF_CLK/10 0 0 1 0 0 fREF_CLK/8 0 0 1 0 1 fREF_CLK/12 0 0 1 1 0 fREF_CLK/16 0 0 1 1 1 fREF_CLK/20
©2016 Integrated Device Technology, Inc Revision E January 22, 20165 TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 165 mA ICCA Analog Supply Current 15 mA TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage CLK1 2 V CC+ 0.3 V CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR CC+ 0.3 V VIL Input Low Voltage CLK1 -0.3 1.3 V CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR -0.3 0.8 V I IH Input High Current CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx V CC = VIN = 3.465V 150 µA PLL_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx V CC = 3.465V, VIN = 0V -5 µA PLL_SEL VCC = 3.465V, VIN = 0V -150 µA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5 V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 42.3°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C All parameters measured at fMAX unless noted otherwise. when the PLL is locked and the input reference frequency is stable. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 4: All outputs in divide by 4 confi guration. TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C NOTE 1: For single ended applications, the maximum input voltage for FB_IN, nFB_IN is VCC + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
©2016 Integrated Device Technology, Inc Revision E January 22, 20167 PARAMETER MEASUREMENT INFORMATION CYCLE-TO-CYCLE JITTER STATIC PHASE OFFSET OUTPUT RISE/FALL TIME DIFFERENTIAL INPUT LEVEL OUTPUT SKEW 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
This section provides information on power dissipation and junction temperature for the 8732-01. Equations and example calculations are also provided. The total power dissipation for the 8732-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 165mA = 572mW
- Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30mW = 300mW Total Power_MAX (3.465V, with all outputs switching) = 572mW + 300mW = 872mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute)
TABLE 8. THERMAL RESISTANCE θJA FOR 52-PIN LQFP, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
- For logic high, V OUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V
- For logic low, V OUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 10. PACKAGE DIMENSIONS
TABLE 11. ORDERING INFORMATION
©2016 Integrated Device Technology, Inc Revision E January 22, 201616 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T4A Features Section - changed VCO min. from 200MHz to 250MHz. Pin Characteristics Table - changed C IN from max. 4pF to typical 4pF . Qx Output Frequency Table - changed the CLK1 min. column to correlate with the VCO change. Absolute Maximum Ratings - changed V O to IO and included Continuous Current and Surge Current Added Differential Clock Input Interface in the Application Information section. 5/20/03 C T5A 5 Power Supply DC Characteristics Table - changed IEE from 240mA max. to 165mA max., and ICCA from 14mA max. to 15mA max. Power Considerations - recalculated Power Dissipation and Junction Tempera- tures to correspond with Table 5A. 6/23/03 C 8 Updated LVPECL Output Termination diagrams. Added Schematic Layout. 9/24/03 C 1 Block Diagram - changed REF_SEL to CLK_SEL. 3/3/04 C T4A 4 Qx Output Frequency Table - changed NOTE 2 from “200MHz” to “175MHz”. 10/19/04 C T11 Features Section - added Lead Free bullet. Ordering Information Table - added Lead Free part number and note. 5/23/05 C T5A 5 Power Supply DC Characteristics Table - corrected I EE to read ICC. 5/31/05 D T5D 6 11 - 12 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO - 0.9V. Power Considerations - corrected power dissipation to refl ect V OH max in Table 5D. 4/13/07 E T11 15 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/31/10 E T5D 9 VOH Maximum = V CCO - 0.9 5/2/13 E T11 15 Removed ICS in the part number where needed. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Update header and footer. 1/22/16
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