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Low SKEW, 1-to-11 Differential-to-3.3V LVPECL Clock Multiplier / Zero Delay Buffer 8731-01 DATA SHEET 8731-01 REVISION B 7/14/15 1 ©2015 Integrated Device Technology, Inc. BLOCK DIAGRAM P IN ASSIGNMENT

FEATURES

  • Eleven differential 3.3V LVPECL outputs
  • Differential reference clock input pair
  • REF_CLK, nREF_CLK pair can accept the following differ- ential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 700MHz
  • Maximum reference clock input frequency: 200MHz
  • VCO range: 250MHz - 700MHz
  • Accepts any single-ended input signal with a resistor bias on nCLK input
  • External feedback for zero delay capabilitiy
  • Output skew: 70ps (maximum)
  • Cycle-to-cycle jitter: 65ps (maximum)
  • Full 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free RoHS compliant package 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View GENERAL DESCRIPTION The 8731-01 is a low voltage, low skew, 1-to-11 Differential-to-3.3V LVPECL Clock Multiplier/Zero Delay Buffer . With output frequencies up to 700MHz the 8731-01 is targeted at high performance clock applications. Along with a fully integrated PLL the 8731- 01 contains frequency configurable, differential out- puts and external feedback inputs for multiplying clock frequencies and regenerating clocks with “zero delay”. Frequency multiplication is achieved by utilizing the separate feedback and clock output dividers. The value of the multiplier is determined by the ratio of the feedback divider, M, to the output divider,N. For multiplier values greater than 1, M must be greater than N. For multiplier values less than 1,M must be less than N. The zero delay mode is achieved with M and N at equal values. The divide values of the clock and feedback outputs are controlled by the DIV_SEL0:2 and FB_SEL0:1 inputs, respectively. The 8731-01 accepts any differential signal and translates it to differential 3.3V LVPECL output levels.

2 REVISION B 7/14/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS

1 MR Input Pulldown

are enabled. LVCMOS / LVTTL interface levels. CCO Power Output supply pins. Q9, nQ9 Output Differential output pairs. 31, 43 VEE Power Negative supply pins. nQ10/nFB_OUT Output Differential clock outputs. 15 V CC Power Core supply pin. 16 FB_SEL0 Input Pulldown Determines output divider for Q10/FB outputs (see Table 3). LVCMOS / LVTTL interface levels. 17 FB_SEL1 Input Pulldown Determines output divider for Q10/FB outputs (see Table 3). LVCMOS / LVTTL interface levels. 18 nREF_CLK Input Pullup Inverting differential clock input. 19 REF_CLK Input Pulldown Non-inverting differential clock input. CCA Power Analog supply pin. 22 DIV_SEL0, Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 23 DIV_SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 24 DIV_SEL2 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 13, 25 nc Unused No connect. Q1, nQ1 Output Differential output pairs. Q3, nQ3 Output Differential output pairs.

37 PLL_SEL Input Pullup

Selects between the PLL and reference clock as the input to the dividers. Q5, nQ5 Output Differential output pairs. Q7, nQ7 Output Differential output pairs. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE FOR Q0:Q9 OUTPUTS Inputs Outputs MR PLL_SEL DIV_SEL2 DIV_SEL1 DIV_SEL0 Q0:Q9, nQ0:nQ9 1X X X X L o w 0 1100 fVCO/1 0 1000 fVCO/2 0 1001 fVCO/4 0 1010 fVCO/6 0 1011 fVCO/8 0 0100 fREF_CLK/1 0 0000 fREF_CLK/2 0 0001 fREF_CLK/4 0 0010 fREF_CLK/6 0 0011 fREF_CLK/8 TABLE 3B. CONTROL INPUT FUNCTION TABLE FOR Q10/FB Inputs Outputs MR PLL_SEL FB_SEL1 FB_SEL0 Q10/FB, nQ10/FB

1 X X X Low

0 0 0 0 fREF_CLK/2 0 0 0 1 fREF_CLK/4 0 0 1 0 fREF_CLK/6 0 0 1 1 fREF_CLK/8 TABLE 3C. QX OUTPUT FREQUENCY W/FB_IN = Q10/FB Inputs fVCO FB_IN FB_SEL1 FB_SEL0 Q10/FB Output Divider Mode REF_CLK (MHz) (NOTE 1)Minimum Maximum Q10/FB 0 0 ÷2 125 200 (NOTE 2) fREF_CLK x 2 Q10/FB 0 1 ÷4 62.5 175 fREF_CLK x 4 Q10/FB 1 0 ÷6 41.67 116.67 fREF_CLK x 6 Q10/FB 1 1 ÷8 31.25 87.5 fREF_CLK x 8 NOTE 1: VCO frequency range is 250MHz to 700MHz. NOTE 2: The maximum input frequency that the phase defector can accept is 200MHz.

LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER 8731-01 DATA SHEET

4 REVISION B 7/14/15

Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 195 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage PLL_SEL, DIV_SEL0, DIV_SEL1, DIV_SEL2, FB_SEL0, FB_SEL1, MR CC + 0.3 V VIL Input Low Voltage PLL_SEL, DIV_SEL0, DIV_SEL1, DIV_SEL2, FB_SEL0, FB_SEL1, MR -0.3 0.8 V I IH Input High Current DIV_SEL0, DIV_SEL1, DIV_SEL2, MR, FB_SEL0, FB_SEL1 V CC = VIN = 3.465V 150 µA PLL_SEL V CC = VIN = 3.465V 5 µA IIL Input Low Current DIV_SEL0, DIV_SEL1, DIV_SEL2, MR, FB_SEL0, FB_SEL1 V CC = 3.465V, VIN = 0V -5 µA PLL_SEL VCC = 3.465V, VIN = 0V -150 µA TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V CC 4.6V Inputs, V I -0.5V to V CC + 0.5V Outputs, I O Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defi ned as VIH. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. when the PLL is locked and the input reference frequency is stable. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C

LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER 8731-01 DATA SHEET

6 REVISION B 7/14/15

PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD STATIC PHASE OFFSET (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset

LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER 8731-01 DATA SHEET

8 REVISION B 7/14/15

FIGURE 3C. REF_CLK/nREF_CLK I NPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3B. REF_CLK/nREF_CLK I NPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. REF_CLK/nREF_CLK I NPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The REF_CLK /nREF_CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the REF_CLK/nREF_CLK input driven by the most common driver types. The input interfaces suggested here are examples FIGURE 3A. REF_CLK/nREF_CLK I NPUT DRIVEN BY LVHSTL DRIVER only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 3A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V

9 LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, termi- nating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. TERMINATION FOR LVPECL OUTPUTS FIGURE 4B. LVPECL OUTPUT TERMINATIONFIGURE 4A. LVPECL OUTPUT TERMINATION INPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVPECL OUTPUT All unused LVPECL outputs can be left fl oating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left fl oating or terminated.

10 REVISION B 7/14/15

FIGURE 5. APPLICATION SCHEMATIC EXAMPLE LVPECL Termination Application Note.

This section provides information on power dissipation and junction temperature for the 8731-01. Equations and example calculations are also provided. The total power dissipation for the 8731-01 is the sum of the core power plus the power dissipated in the load(s). CC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

  • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 195mA = 675.67mW
  • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 11 * 30mW = 330mW Total Power_MAX (3.465V, with all outputs switching) = 675.67mW + 330mW = 1005.67mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (single layer or multi-layer). θJA by Velocity (Linear Feet per Minute)

TABLE 7. THERMAL RESISTANCE θJA FOR 48-PIN LQFP, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

12 REVISION B 7/14/15

  1. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION

TABLE 8. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

14 REVISION B 7/14/15

TABLE 9. PACKAGE DIMENSIONS

TABLE 10. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL CLOCK MULTIPLIER / ZERO DELAY BUFFER 8731-01 DATA SHEET

16 REVISION B 7/14/15

Rev Table Page Description of Change Date A T10 Features Section - added Lead-Free bullet . Ordering Information Table - added Lead-Free part number, marking and note. 6/6/06 B T10 15 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/27/10 Updated data sheet format. 7/14/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.