872S480BKLF

ICS872S480 IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 20

Technical content

Features

• Three differential HSTL output pairs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL
• Output frequency range: 350MHz to 950MHz
• Input frequency range: 350MHz to 950MHz
• VCO range: 970MHz to 2250MHz
• External feedback for “zero delay” clock regeneration with configurable frequencies
• Static phase offset: ±100ps (maximum)
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 20ps (maximum)
• 3.3V operating voltage supply
• Selectable DDR3 or DDR3 low voltage output
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package ICS872S480 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View Pin Assignment Function Table Input Output Divider Input & Output Frequency (MHz) FREQ_SEL Minimum Maximum 0 2 485 950 1 (default) 4 350 562.5 Output Voltage Table Input HSTL Output StyleVOUT_SEL 0 (default) 1.5V 1 1.35V

ICS872S480BK REVISION A APRIL 19, 2011 2 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR Block Diagram PD CP LF PLL_Bypass Output Divider Activity Detector Activity Detector Dynamic Switch Logic 1 LOR0 LOR1 REF_SEL AUTO_SEL VCO OE QFB, nQFB Q0, nQ0 Q1, nQ1 FREQ_SEL CLK_IND VOUT_SEL Pulldown Pulldown Pulldown Pullup Pullup Pullup CLK0 nCLK0 Pullup Pulldown Pullup Pulldown Pullup Pulldown CLK1 nCLK1 FB_IN nFB_IN

ICS872S480BK REVISION A APRIL 19, 2011 3 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK0 Input Pulldown Non-inverting differential clock input. 2 nCLK0 Input Pullup Inverting differential clock input. 3, 20, 28 GND Power Power supply ground. 4 CLK1 Input Pulldown Non-inverting differential clock input. 5 nCLK1 Input Pullup Inverting differential clock input. passed directly to the output dividers. LVCMOS/LVTTL interface levels. 7 FB_IN Input Pulldown Non-inverting differential external feedback input. 8 nFB_IN Input Pullup Inverting differential external feedback input. 9, 10 nQFB, QFB Output Differentia l feedback output pair. HSTL interface levels. See Table 4D. 25, 32 VDD Power Core supply pins. 12, 13 nQ1, Q1 Output Differential outp ut pair. HSTL interface levels. 14, 15 nQ0, Q0 Output Differential outp ut pair. HSTL interface levels. 17 V DDA Power Analog supply pin. 18 OE Input Pullup Output enable pin. LVCMOS/LVTTL interface levels. 19 FREQ_SEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels. 22 LOR1 Output Loss of Reference Indicator for CL K1, nCLK1. LVCMOS/LVTTL interface levels. 23 LOR0 Output Loss of Reference Indicator for CL K0, nCLK0. LVCMOS/LVTTL interface levels. 26 VOUT_SEL Input Pulldown Output voltage select pi n. LVCMOS/LVTTL interface levels. 27, 29 nc Unused No connect.

30 AUTO_SEL Input Pullup

Clock Switch is enabled. LVCMOS/LVTTL interface levels. CLK1, nCLK1. LVCMOS/LVTTL interface levels.

ICS872S480BK REVISION A APRIL 19, 2011 4 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 42.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage V DD –0.25 3.3 V DD V IDD Power Supply Current Outputs terminated 50 Ω to GND 275 mA IDDA Analog Supply Current 25 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current PLL_BYPASS, REF_SEL, VOUT_SEL VDD = VIN = 3.465V 150 µA OE, FREQ_SEL, AUTO_SEL VDD = VIN = 3.465V 10 µA IIL Input Low Current PLL_BYPASS, REF_SEL, VOUT_SEL V DD = 3.465V, VIN = 0V -10 µA OE, FREQ_SEL, AUTO_SEL VDD = 3.465V, VIN = 0V -150 µA

ICS872S480BK REVISION A APRIL 19, 2011 5 ©2011 Integrated Device Technology, Inc. NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. NOTE 1: Outputs terminated with 50Ω to ground. Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C

ICS872S480BK REVISION A APRIL 19, 2011 6 ©2011 Integrated Device Technology, Inc. Table 6. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. the PLL is locked and the input reference frequency is stable. Characterized using HSTL input level of 900mV, swing centered around 0.6V. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. phase. This does not factor in any cycle-to-cycle jitter seen on the input or output. NOTE 5: Output slew rate is measured at VOX ± 150mV for VOUT_SEL = 0 and VOX ±135mV for VOUT_SEL = 1. NOTE 6: This parameter is defined as PLL lock time after a dynamic switch event with reference inputs 180° out of phase. NOTE 7: This parameter is guaranteed by characterization. Not tested in production.

ICS872S480BK REVISION A APRIL 19, 2011 7 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V Output Load AC Test Circuit Cycle-to-Cycle Jitter Static Phase Offset Differential Input Level Output Skew Output Duty Cycle/Pulse Width/Period SCOPE HSTL Qx nQx GND VDDA 3.3V ± 5% 3.3V ± 5% VDD nQ[0:1] Q[0:1] ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

nCLK[0:1] CLK[0:1] nFB_IN FB_IN ➤ ➤t(Ø) t(Ø)mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on controlled edges) nCLK0, nCLK1 CLK0, CLK1 VDD GND VCMR Cross Points VPP nQx Qx nQy Qy tsk(o) tPW tPERIOD tPW tPERIOD odc = x 100% nQ[0:1] Q[0:1]

ICS872S480BK REVISION A APRIL 19, 2011 8 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued Dynamic Phase Offset Slew Rate PLL Lock Time ➤ ➤t(Ø) Histogram Dynamic Phase Offset Dynamic Phase Offset =  t(Ø) – t(Ø)mean tdyn(Ø) = Peak-to-Peak value of Dynamic Phase Offset Histogram Where t(Ø) is any random sample, and t(Ø)mean is the average of the sampled cycles measured on the controlled edges ➤ t(Ø)mean nCLK[0:1] nCLK[0:1] nFB_IN FB_IN ∆t∆t VOX +VAC -VAC VAC = 150mV for VOUT_SEL = 0 VAC = 135mV for VOUT_SEL = 1 2 * VAC ∆ttSLEW = VOD

ICS872S480BK REVISION A APRIL 19, 2011 9 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR Applications Information Clock Redundancy and Reference Selection The ICS872S480 accepts two differential input clocks, CLK0, nCLK0 and CLK1, nCLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. CLK0, nCLK0 is defined as the initial, or primary clock, while the remaining clock is the redundant or secondary clock. The output signal CLK_IND indicates which clock input is being used as the reference (LOW = CLK0, nCLK0, HIGH = CLK1, nCLK1). Failure Detection and Alarm Signaling Within the ICS872S480 device, CLK0, nCLK0 and CLK1, nCLK1 are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period of the feedback. Upon detection of a failure, the corresponding loss-of-reference signal, LOR0 or LOR1, will be set HIGH. The input clocks are continuously monitored and the loss-of-reference signals will continue to reflect the real-time status of each input clock. Manual Clock Switching When input signal AUTO_SEL is driven LOW, the clock specified by REF_SEL will always be used as the reference, even when a clock failure is detected at the reference. In order to switch between CLK0, nCLK0 and CLK1, nCLK1 as the reference clock, the level on REF_SEL must be driven to the appropriate level. When the level on REF_SEL is changed, the selection of the new clock will take place, and CLK_IND will be updated to indicate which clock is now supplying the reference to the PLL. Dynamic Clock Switching The Dynamic Clock Switching (DCS) process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. When input signal AUTO_SEL is not driven HIGH, an internal pullup pulls it HIGH so that DCS is enabled. If DCS is enabled and a failure occurs on the initial clock, the ICS872S480 device will check the status of the secondary clock. If the secondary clock is detected as a good input clock, the ICS872S480 will automatically de-select the initial clock as the reference and multiplex in the secondary clock. When a successful switch from the initial to secondary clock has been accomplished, CLK_IND will be updated to indicate the new reference. If and when the fault on the initial clock is corrected, the corresponding loss-of-reference flag will be updated to represent this clock as good again. Once updated, the DCS will undergo an automatic clock switch. See the Dynamic Clock Switch State Diagram and for additional details on the functionality of the Dynamic Clock Switching circuit. Output Transitioning After a successful DCS initiated clock switch, the internal PLL of the ICS872S480 will begin slewing to phase/frequency alignment of the newly selected clock input. The PLL will achieve lock to the new input with minimal phase disturbance at the outputs. Recommended Power-up Sequence 1.Before startup, set AUTO_SEL low so the PLL will operate in manual switch mode, plus set REF_SEL low to ensure that the primary reference clock, CLK0, nCLK0, is selected. This will ensure that during startup, the PLL will acquire lock using the primary reference clock input. 2.Once powered-up, and assuming a stable clock is present at the primary clock input, the PLL will begin to phase/frequency slew as it attempts to achieve lock with the input reference clock. 3.Drive AUTO_SEL HIGH to enable DCS mode. Alternate Power-up Sequence If both input clocks are valid before power up, the part may be powered-up in DCS mode. However, it cannot be guaranteed that the PLL will achieve lock with one specific input clock. 1.Before startup, leave AUTO_SEL floating and the internal pullup will enable DCS mode. 2.Once powered up, the PLL will begin to phase/frequency slew as it attempts to achieve lock with one of the input reference clocks.

ICS872S480BK REVISION A APRIL 19, 2011 10 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR State Diagram

ICS872S480BK REVISION A APRIL 19, 2011 13 ©2011 Integrated Device Technology, Inc. resistance is not required but can be added for additional protection. additional protection, a 1kΩ resistor can be tied from CLK to ground. should either be left floating or terminated. Figure 4. Output Termination

ICS872S480BK REVISION A APRIL 19, 2011 14 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS872S480BK REVISION A APRIL 19, 2011 16 ©2011 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS872S480. Equations and example calculations are also provided. The total power dissipation for theICS872S480 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 42.7°C/W per Table 7 below. Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection

ICS872S480BK REVISION A APRIL 19, 2011 17 ©2011 Integrated Device Technology, Inc. Table 8. θJA vs. Air Flow Table for a 32-lead VFQFN

ICS872S480BK REVISION A APRIL 19, 2011 18 ©2011 Integrated Device Technology, Inc. Table 9. Package Dimensions package dimensions are in Table 9.

1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)

ICS872S480BK REVISION A APRIL 19, 2011 19 ©2011 Integrated Device Technology, Inc. ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR

Ordering Information

Table 10. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

ICS872S480 Data Sheet DIFFERENTIAL-TO -HSTL ZERO DELAY CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 We’ve Got Your Timing Solution