8725B-21 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: epieczon
- PDF pages: 16
Technical content
Features
One differential HSTL output pair One differential feedback output pair Differential CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL Output frequency range: 31.25MHz to 630MHz Input frequency range: 31.25MHz to 630MHz VCO range: 250MHz to 630MHz External feedback for “zero delay” clock regeneration with configurable frequencies Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Cycle-to-cycle jitter: 50ps (maximum) Output skew: 50ps (maximum) Static phase offset: 200ps (maximum) 3.3V core, 1.8V output operating supply 0°C to 70°C ambient operating temperature Block Diagram Pin Assignment PLL_SEL CLK nCLK FB_IN nFB_IN SEL0 SEL1 SEL2 SEL3 MR Q nQ QFB nQFB PLL 1:2, 1:4, 1:8 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 Pullup Pullup Pulldown Pullup Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pulldown Pulldown nQFB GND SEL2 FB_IN nFB_IN VDD MR nCLK CLK QFB nc SEL1 SEL0 VDD PLL_SEL VDDA SEL3 VDDO Q nQ 8725B-21 20-Lead SOIC 7.5mm x 12.8mm package body
Table 2. Pin Characteristics Table 1. Pin Descriptions1 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
are enabled. LVCMOS / LVTTL interface levels. 4V DD Power Core supply pins. clocks with “Zero Delay.” Connect to pin 9.
6 FB_IN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 10. 8 GND Power Power supply ground. 9 nQFB Output Inverting differential feedback output. HSTL interface levels. 10 QFB Output Non-inverting differential feedback output. HSTL interface levels. 11 nQ Output Inverting differential output. HSTL interface levels. 12 Q Output Non-inverting differential output. HSTL interface levels. DDO Power Output supply pin. 15 VDDA Power Analog supply pin.
16 PLL_SEL Input Pullup
LVCMOS/LVTTL interface levels. 17 VDD Power Core supply pins. NOTE 1.Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION 1 11/12/15 3 DIFFERENTIAL- TO-HSTL ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q, nQ 0000 250 - 630 ÷1 0001 125 - 315 ÷1 0010 6 2 . 5 - 1 5 7 . 5 ÷ 1 0011 3 1 . 2 5 - 7 8 . 7 5 ÷ 1 0100 250 - 630 ÷2 0101 125 - 315 ÷2 0110 6 2 . 5 - 1 5 7 . 5 ÷ 2 0111 250 - 630 ÷4 1000 125 - 315 ÷4 1001 250 - 630 ÷8 1010 125 - 315 x2 1011 6 2 . 5 - 1 5 7 . 5 x 2 1100 3 1 . 2 5 - 7 8 . 7 5 x 2 1101 6 2 . 5 - 1 5 7 . 5 x 4 1110 3 1 . 2 5 - 7 8 . 7 5 x 4 1111 3 1 . 2 5 - 7 8 . 7 5 x 8 Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q, nQ, QFB, nQFB 0000 ÷ 4 0001 ÷ 4 0010 ÷ 4 0011 ÷ 8 0100 ÷ 8 0101 ÷ 8 0110 ÷ 1 6 0111 ÷ 1 6 1000 ÷ 3 2 1001 ÷ 6 4 1010 ÷ 2 1011 ÷ 2 1100 ÷ 4 1101 ÷ 1 1110 ÷ 2 1111 ÷ 1
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR 4 REVISION 1 11/12/15 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 46.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Junction Temperature 125°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SEL[0:3], MR VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 5 µA IIL Input Low Current SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V, VIN = 0V -150 µA Item Rating Table 4A. Power Supply DC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 137 mA IDDA Analog Supply Current 17 mA IDDO Output Supply Current No Load 0 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units
Table 5. Input Frequency Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C NOTE 1. V IL should not be less than -0.3V. NOTE 2. Common mode input voltage is defined as V IH. NOTE 1. Outputs termination with 50 to ground. NOTE 2. Defined with respect to output voltage swing at a given condition.
Table 6. AC Characteristics, VDD = VDDA = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C1, 2 equilibrium has been reached under these conditions. NOTE 2. All parameters measured at f MAX unless noted otherwise. NOTE 3. Measured from the differential input crossing point to the differential output crossing point. and the input reference frequency is stable. NOTE 5. This parameter is defined in accordance with JEDEC Standard 65. NOTE 7. Characterized at VCO frequency of 622MHz. NOTE 8. Phase jitter is dependent on the input source used.
REVISION 1 11/12/15 7 DIFFERENTIAL- TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V Core/1.8V Output Load AC Test Circuit Differential Input Level Cycle-to-Cycle Jitter Output Rise/Fall Time Phase Jitter and Static Phase Offset Output Skew Output Pulse Width Propagation Delay SCOPE Qx nQx HSTL GND VDDA VDDO VDD, 3.3V±5% 1.8V±0.2V GND = 0V nCLK CLK VDD GND V CMR Cross Points V PP nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
20% 80% 80% 20% tR tF VSWINGVOX nQ Q nCLK CLK nFBIN FBIN ➤ ➤t(Ø) VOH VOL VOH VOL tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges) nQx Qx nQFB QFB Pulse Width tPERIOD nQ Q tPD nCLK CLK nQ, nQFB Q, QFB
Equations and example calculations are also provided. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. maximum recommended junction temperature for is 125°C. flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 39.7°C/W per Table 7 below. board (single layer or multi-layer). Table 7. Thermal Resistance JA for 20-Lead SOIC, Forced Convection1 NOTE 1. Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 4. Figure 4. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 8. JA vs. Air Flow Table for a 20-Lead TSSOP1 NOTE 1. Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Table 9. Package Dimensions for 20-Lead SOIC
300 Millimeters
DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR 14 REVISION 1 11/12/15
Ordering Information
Table 10. Ordering Information
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