871002AGI-02LFT

871002AGI-02LF IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

Features

• Two 0.7V HCSL differential output pairs
• One differential clock input
• CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
• Input frequency range: 98MHz to 128MHz
• Output frequency range: 98MHz to 640MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 45ps (maximum)
• Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages PLL Bandwidth (typical) Table HiPerClockS™ ICS BW_SEL 0 = PLL Bandwidth: ~350kHz (default) 1 = PLL Bandwidth: ~2200kHz ÷5 (fixed) VCO 490 - 640 MHz Phase Detector Output Divider 00 ÷5 01 ÷4 10 ÷2 (default) 11 ÷1 nQ0 nQ1 FB_OUT nFB_OU BW_SEL CLK nCLK FB_IN nFB_IN F_SEL[1:0] MR OE Pulldown Pullup:Pulldown Pulldown Pullup Pullup Pulldown Pullup Pulldown IREF 0 = 350kHz 1 = 2200kHz F_SEL0 VDDA F_SEL1 BW_SEL MR nFB_OUT FB_OUT IREF nQ0 VDD VDD nQ1 nFB_IN FB_IN GND nCLK CLK OE Pin Assignment ICS871002I-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Block Diagram

ICS871002AGI-02 REVISION A APRIL 14, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 20 nQ0, nQ0 Output Differential output pair. HCSL interface levels.

2 IREF Input A fixed precision resistor (475Ω) from this pin to ground provides a reference

current used for differential current-mode Qx/nQx clock outputs. nFB_OUT Output Differential feedback output pair. HCSL interface levels.

5 MR Input Pulldown

enabled. LVCMOS/LVTTL interface levels. 6 BW_SEL Input Pulldown PLL Bandwidth select i nput. 0 = 350kHz, 1 = 2200kHz. See Table 3B. 8V DDA Power Analog supply pin. 10, 19 V DD Power Core supply pins. in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. 12 CLK Input Pulldown Non-inverting differential clock input. 13 nCLK Input Pullup Inverting differential clock input. 14 GND Power Power supply ground. 15 FB_IN Input Pulldown Non-inverting differential feedback clock input. 16 nFB_IN Input Pullup Inverting differential feedback clock input. 17, 18 nQ1, Q1 Output Differential output pair. HCSL interface levels.

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS871002AGI-02 REVISION A APRIL 14, 2010 3 ©2010 Integrated Device Technology, Inc. Function Tables Table 3A. Output Enable Function Table Table 3B. PLL Bandwidth Control Table Table 3C. F_SELx Function Table Input Outputs OE Q[1:0], nQ[1:0] FB_OUT, nFB_OUT

0 High-Impedance Enabled

1 (default) Enabled Enabled Input PLL BandwidthBW_SEL 0 350kHz (default) 1 2200kHz Input Frequency (MHz) Inputs Output Frequency (MHz)F_SEL1 F_SEL0 Divider 100 0 0 ÷5 100 100 0 1 ÷4 125 100 1 0 ÷2 250 (default) 100 1 1 ÷1 500

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS871002AGI-02 REVISION A APRIL 14, 2010 4 ©2010 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 86.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.97 3.3 3.63 V VDDA Analog Supply Voltage V DD – 0.12 3.3 V DD V IDD Power Supply Current 75 mA IDDA Analog Supply Current 12 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current OE, F_SEL1 V DD = VIN = 3.63V 5 µA BW_SEL, F_SEL0, MR VDD = VIN = 3.63V 150 µA IIL Input Low Current OE, F_SEL1 V DD = 3.63V, VIN = 0V -150 µA BW_SEL, F_SEL0, MR V DD = 3.63V, VIN = 0V -5 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK, FB_IN V DD = VIN = 3.465V 150 µA nCLK, nFB_IN V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK, FB_IN V DD = 3.465V, VIN = 0V -5 µA nCLK, nFB_IN V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

ICS871002AGI-02 REVISION A APRIL 14, 2010 5 ©2010 Integrated Device Technology, Inc. Table 5. 0.7V HCSL Differential AC Characteristics, VDD = 3.3V ± 10%, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at f ≤ 250MHz unless noted otherwise. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Measurement taken from single ended waveform. NOTE 3: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 4: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 5: Measurement taken from differential waveform. allowed to drop back into the VRB ±100mV differential range. NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ. points for this measurement. NOTE 10: Input duty cycle must be 50%.

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS871002AGI-02 REVISION A APRIL 14, 2010 6 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V HCSL Output Load AC Test Circuit Differential Input Level Differential Measurement Points for Duty Cycle/Period 3.3V HCSL Output Load AC Test Circuit Cycle-to-Cycle Jitter Differential Measurement Points for Ringback 475Ω Measurement Point33Ω 50Ω 50Ω33Ω Measurement Point 49.9Ω 49.9Ω HCSL GND 2pF 2pF IREF VDDA VDD 3.3V±10% 3.3V±10% nCLK, CLK, VDD GND V CMR Cross Points V PP nFB_IN FB_IN Clock Period (Differential) Positive Duty Cycle (Differential) Negative Duty Cycle (Differential) Q - nQ 0.0V 475Ω 50Ω 50Ω HCSL GND SCOPE IREF This load condition is used for IDD and tjit(cc) measurements. 3.3V±10% VDDA 3.3V±10% VDD nQ[0:1], nFB_OUT Q[0:1], FB_OUT ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

-150mV VRB = -100mV VRB = +100mV +150mV 0.0V

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS871002AGI-02 REVISION A APRIL 14, 2010 7 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information, continued Single-ended Measurement Points for Absolute Cross Point and Swing Output Rise/Fall Time Single-ended Measurement Points for Delta Cross Point nQ Q VCROSS_MAX = 550mV VCROSS_MIN = 250mV VMAX = 1.15V VMIN = -0.30V Q - nQ -150mV +150mV 0.0V Fall Edge RateRise Edge Rate Q nQ VCROSS_DELTA = 140mV

ICS871002AGI-02 REVISION A APRIL 14, 2010 12 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS871002I-02. Equations and example calculations are also provided. The total power dissipation for the ICS71002I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

ICS871002AGI-02 REVISION A APRIL 14, 2010 13 ©2010 Integrated Device Technology, Inc. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 6. Figure 6. HCSL Driver Circuit and Termination use the following equations which assume a 50Ω load to ground. The highest power dissipation occurs when VDD_MAX.

ICS871002AGI-02 REVISION A APRIL 14, 2010 14 ©2010 Integrated Device Technology, Inc. Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR ICS871002AGI-02 REVISION A APRIL 14, 2010 15 ©2010 Integrated Device Technology, Inc.

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS871002I-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2010. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056