870919I-01 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 16
Technical content
Features
- Two selectable single-ended input reference clocks
- Eight single-ended clock outputs
- Internal PLL does not require external loop filter components
- 5V tolerant inputs
- Maximum output frequency: 160MHz, (2XQ output)
- Maximum output frequency: 80MHz, (Q0:Q4 and nQ5 outputs)
- LVCMOS interface levels for all inputs and outputs
- PLL disable feature for low-frequency testing
- PLL lock output
- Selectable synchronization of output to input edge
- Output drive capability: ±24mA
- Output skew: 300ps (maximum), Q0:Q4
- Output skew: 500ps (maximum), all outputs
- Full 3.3V supply voltage
- Available in lead-free packages
- -40°C to 85°C ambient operating temperature
- Fully pin and function compatible with the IDT QS5LV919 (including 55, 70, 100, 133 and 160MHz options)
- For functional replacement part use 8T49N285 Block Diagram SYNC0 SYNC1 REF_SEL FEEDBACK nPE PLL_EN FREQ_SEL OE/nRST fREF PLL 20MHz - 160MHz fVCO LOCK 2XQ nQ5 Q/2
REVISION C 11/6/15 2 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Pin Assignments 12 13 14 15 16 17 18 4 3 2 1 28 27 26 FEEDBACK REF_SEL SYNC0 AVDD nPE AGND SYNC1 VDD GND GND Q/2 LOCK FREQ_SEL PLL_EN VDD GND GND 2XQ GND nQ5 OE/nRST VDD VDD FEEDBACK REF_SEL SYNC0 AVDD nPE AGND SYNC1 VDD GND GND Q/2 LOCK FREQ_SEL PLL_EN VDD GND GND 2XQ Q4GND nQ5 OE/nRST VDD VDD 870919I-01 28-Lead QSOP, 150Mil 3.9mm x 9.9mm x 1.5mm package body R Package Top View 870919I-01 28-Lead PLCC 11.5mm x 11.5mm x 4.4mm package body V Package Top View
Table 1. Pin Descriptions NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 13, 17, 20, 24 GND Power Power supply ground. 2 nQ5 Output Single-ended clock output (phase is inverted with respect to other outputs). 3, 15, 22, 27 V DD Power Positive power supply pins.
4 OE/nRST Input
outputs are in a high impedance state. Logic HIGH enables all outputs. asynchronously to the input reference.
5 FEEDBACK Input PLL feedback input which is connected to one of the clock outputs to close the
PLL feedback loop. LVCMOS/LVTTL interface levels.
6 REF_SEL Input
Input reference clock select. Logic LOW selects the SYNC0. Logic HIGH selects the SYNC1 input as the PLL reference input. LVCMOS/LVTTL interface levels. SYNC1 Input Single-ended reference clock inputs. LVCMOS/LVTTL interface levels. 8A V D D P o w e r Positive power supply for the PLL. the rising edge of the selected reference clock (SYNCn). reference clock (SYNCn). LVCMOS/LVTTL interface levels. 10 AGND Power Power supply ground for the PLL. Internally connected to GND.
12 FREQ_SEL Input
feedback path. LVCMOS/LVTTL interface levels. Q2, Q3, Q4 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels.
18 PLL_EN Input
dividers (PLL bypass). LVCMOS/LVTTL interface levels. PLL is not locked. LVCMOS/LVTTL interface levels. 25 Q/2 Output Single-ended clock output. LVCMOS/LVTTL interface levels. 26 2XQ Output Single-ended clock output. LVCMOS/LVTTL interface levels.
Table 2. Pin Characteristics ranges. See Table 3G for details. 0 Device is reset and the outputs Q0:Q4, nQ5, 2XQ, Q/2 are in high-impedance state. This control is asynchronous. 0 SYNC0 is the selected PLL reference clock. 1 SYNC1 is the selected PLL reference clock. 0 The rising edge of the 2XQ, Q0:Q4 and Q/2 outputs and the falling edge of the nQ5 output are synchronized. 1 The falling edge of the 2XQ, Q0:Q4 and Q/2 outputs and the rising edge of the nQ5 output are synchronized.
LVCMOS CLOCK GENERATOR 5 REVISION C 11/6/15 870919I-01 DATA SHEET Table 3D. FREQ_SEL Mode Configuration Table Table 3E. PLL_EN Mode Configuration Table Table 3F. LOCK Mode Configuration Table Table 3G. Frequency Configuration Table NOTE 1: The nQ5 output is inverted (180° phase shift) with respect to Q0:Q4. NOTE 2: The input reference frequency is limited to 100MHz maximum. Input OperationFREQ_SEL 0 The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range. See also table 3G for available frequency ranges. 1 The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range. See also table 3G for available frequency ranges. Input OperationPLL_EN 0 The PLL is bypassed. The selected input reference clock is routed to the output dividers for low-frequency board test purpose. The PLL-related AC specifications do not apply in PLL bypass mode. 1 The PLL is enabled and locks to the selected input reference signal. Output OperationLOCK 0 PLL is not locked to the selected input reference clock. 1 PLL is locked to the sele cted input reference clock. Outputs Used for PLL Feedback FREQ_SEL Input Frequency Range (MHz) Output Frequency Range (MHz) and Output-to-Input Frequency Multiplication Factor SYNC[0:1] Q[0:4], nQ5 NOTE1 2XQ Q/2 Q0, Q1, Q2, Q3, Q4 or nQ5 0 5 - 40 5 - 40 (1x) 10 - 80 (2x) 2.5 - 20 (0.5x) 1 10 - 80 10 - 80 (1x) 20 - 160 (2x) 5 - 40 (0.5x) 2XQ 0 10 - 80 5 - 40 (0.5x) 10 - 80 (1x) 2.5 - 20 (0.25x) 1 20 - 100 NOTE2 10 - 50 (0.5x) 20 - 100 (1x) 5 - 25 (0.25x) Q/2 0 2.5 - 20 5 - 40 (2x) 10 - 80 (4x) 2.5 - 20 (1x) 1 5 - 40 10 - 80 (2x) 20 - 160 (4x) 5 - 40 (1x)
REVISION C 11/6/15 6 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Item Rating Supply Voltage, VDD(ABS MAX) 4.6V Inputs, VI -0.5V to VDD(ABS MAX) + 0.5V Outputs, VO -0.5V to VDD(ABS MAX) + 0.5V Package Thermal Impedance, JA
28 Lead QSOP
28 Lead PLCC
66.0°C/W (0 lfpm) 46.4°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD, AVDD Positive Supply Voltage 3.0 3.3 3.6 V IDDQ Quiescent Power Supply Current VDD = AVDD = max., OE/nRST = 0, SYNCx = 0, all outputs open 5m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current FREQ_SEL, FEEDBACK, SYNCn, OE/nRST, REF_SEL, PLL_EN VDD = VIN = 3.3V 5 µA nPE V DD = VIN = 3.3V 150 µA IIL Input Low Current FREQ_SEL, FEEDBACK, nPE, SYNCn, OE/nRST, REF_SEL, PLL_EN V DD = 3.3V, VIN = 0V -5 µA VOH Output High Voltage Q0:Q4, nQ5, 2XQ, Q/2, LOCK IOH = -24mA 2.6 V VOL Output Low Voltage Q0:Q4, nQ5, 2XQ, Q/2, LOCK IOL = 24mA 0.5 V IOZ Output Leakage Current Q0:Q4, nQ5, 2XQ, Q/2 OE/nRST = 0, VOUT = 0V or VDD, VDD = 3.6V ±5µ A
Table 5. AC Electrical Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured between coincident rising output edges of Q0:Q4, 2XQ, Q/2 and the falling edge of nQ5. the input reference frequency is stable. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
REVISION C 11/6/15 8 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Parameter Measurement Information 3.3V Output Load AC Test Circuit Cycle-to-Cycle Jitter Static Phase Offset Output Skew Static Phase Offset Output Pulse Width SCOPE Qx GND VDD, 1.65V±0.15V -1.65V±0.15V AVDD ➤➤ ➤➤tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Q[0:4], nQ5 ➤ ➤ t(Ø) VDD VDD FEEDBACK SYNC[0:1] Static Phase Offset for nPE = 1 tsk(o) tsk(o) tsk(o) Qx Qy Q/2 2xQ ➤ ➤ t(Ø) VDD VDD t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges FEEDBACK SYNC[0:1] Static Phase Offset for nPE = 0 Pulse Width tPERIOD Q[0:4], nQ5, 2XQ, Q/2
REVISION C 11/6/15 9 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Parameter Measurement Information Output Rise/Fall Time Output Enable/Disable
Application Information
Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. 0.8V 2V 2V 0.8V tR tF Q0:Q4, nQ5, Q/2, 2XQ VDD/2 V DD/2 VDD/2 V DD/2 VOL VOH VDD tDIS tEN Output Qx (See Note) OE (High-level enabling)
This section provides information on power dissipation and junction temperature for the 870919I-01. Equations and example calculations are also provided. The total power dissipation for the 870919I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. maximum recommended junction temperature for the devices is 125°C. a multi-layer board, the appropriate value is 66°C/W per Table 6 below. Table 6. Thermal Resistance JA for a 28 Lead QSOP, Forced Convection
REVISION C 11/6/15 12 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Package Outline - R Suffix for 28 Lead QSOP, 150MIL Table 7B. Package Dimensions for 28 Lead QSOP Reference Document: JEDEC Publication 95, MO-137 Reliability Information Table 8A. JA vs. Air Flow Table for a 28 Lead QSOP, 150MIL Table 8B. JA vs. Air Flow Table for a 28 Lead PLCC Transistor Count The transistor count for 870919I-01: 1654 All Dimensions in Millimeters Symbol Minimum Maximum N 28 A 1.35 1.75 A1 0.10 0.25 A2 1.50 b 0.20 0.30 c 0.18 0.25 D 9.80 10.00 E 5.80 6.20 E1 3.80 4.00 e 0.635 Basic L 0.40 1.27 0° 8° ZD 0.84 Ref JA vs. Air Flow Linear Feet per Minute 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 66.0°C/W 58.3°C/W 55.2°C/W JA vs. Air Flow Linear Feet per Minute 0 200 500 Multi-Layer PCB, JEDEC Standard Test Boards 46.4°C/W 38.6°C/W 36.2°C/W
LVCMOS CLOCK GENERATOR 13 REVISION C 11/6/15 870919I-01 DATA SHEET
Ordering Information
Table 9. Ordering Information NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION C 11/6/15 14 LVCMOS CLOCK GENERATOR 870919I-01 DATA SHEET Revision History Sheet Rev Table Page Description of Change Date A 2 QSOP Pin Assignment - added dimensions. 7/7/09 B 3, 6 Updated Pin 4, OE/nRST Description; changed V DD to VDD (ABS MAX). 11/15/11 C 10 Added Application Schematic 1/6/12 C T9 14 Removed leaded orderable parts from the Ordering Information table 11/15/12 C Crossed out PLCC package. Removed PLCC package drawing. Ordering Information - removed PLCC part number. 11/6/15
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