ICS8705 IDT | Alldatasheet
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8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION The ICS8705 is a highly versatile 1:8 Differential-to- LVCMOS/LVTTL Clock Generator. The ICS8705 has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The ICS8705 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following out- put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.
FEATURES
8 LVCMOS/LVTTL outputs, 7Ω typical output impedance Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL CLK0 input accepts LVCMOS or LVTTL input levels Output frequency range: 15.625MHz to 250MHz Input frequency range: 15.625MHz to 250MHz VCO range: 250MHz to 500MHz External feedback for “zero delay” clock regeneration with configurable frequencies Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 Fully integrated PLL Cycle-to-cycle jitter: 45ps (maximum) Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum) Static Phase Offset: 25 ±125ps (maximum), CLK0 Full 3.3V or 2.5V operating supply 0°C to 70°C ambient operating temperature Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32-Lead LQFP 7mm x 7mm x 1.4 mm Y Package Top View VDDO GND V DDO GND SEL0 SEL1 CLK0 nc CLK1 nCLK1 CLK_SEL MR VDDO GND V DDO SEL2 FB_IN V DD GND VDDO SEL3 VDDA PLL_SEL VDD ICS8705 PLL_SEL CLK0 CLK1 nCLK1 CLK_SEL FB_IN SEL0 SEL1 SEL2 SEL3 MR PLL 1:2, 1:4, 1:8 ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128 0
TABLE 1. PIN DESCRIPTIONS TABLE 2. P IN CHARACTERISTICS
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 3A. PLL E NABLE FUNCTION TABLE stupnI stuptuO 0=LES_LLP edoMssapyBLLP 3LES2 LES1 LES0 LES7 Q:0Q 0000 8 ÷ 000 1 8 ÷ 00 10 8 ÷ 00 11 6 1÷ 0100 6 1÷ 0101 6 1÷ 0110 2 3÷ 0111 2 3÷ 10 0 0 4 6÷ 10 0 1 8 21÷ 10 10 4 ÷ 10 1 1 4 ÷ 1100 8 ÷ 110 1 2 ÷ 1110 4 ÷ 1111 2 ÷ TABLE 3B. PLL B YPASS FUNCTION TABLE stupnI stuptuO 1=LES_LLP edoMelbanELLP 3LES2 LES1 LES0 LES) zHM(egnaRycneuqerFecnerefeR7 Q:0Q 0000 0 52-5211 ÷ 000 1 5 21-5.261 ÷ 00 10 5 .26-52.131 ÷ 00 11 5 2.13-526.511 ÷ 01 00 0 52-5212 ÷ 01 01 5 21-5.262 ÷ 011 0 5 .26-52.132 ÷ 0111 0 52-5214 ÷ 10 0 0 5 21-5.264 ÷ 10 0 1 0 52-5218 ÷ 10 10 5 21-5.262 x 10 1 1 5 .26-52.132 x 1100 5 2.13-526.512 x 110 1 5 .26-52.134 x 1110 5 2.13-526.514 x 1111 5 2.13-526.518 x
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 531.33 .35 64.3V V ADD egatloVylppuSgolanA 531.33 .35 64.3V V ODD egatloVylppuStuptuO 531.33 .35 64.3V I DD tnerruCylppuSrewoP 69A m I ADD tnerruCylppuSgolanA 51A m I ODD tnerruCylppuStuptuO 02A m TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI tupnI egatloVhgiH ,LES_KLC,LES_LLP ,3LES,2LES,1LES,0LES RM,NI_BF 2V DD 3.0+V 0KLC2 V DD 3.0+V V LI tupnI egatloVwoL ,LES_KLC,LES_LLP ,3LES,2LES,1LES,0LES RM,NI_BF 3.0-8 .0V 0KLC3 .0-3 .1V I HI tupnI tnerruChgiH LES_KLC,0KLC ,NI_BF,RM 3LES,2LES,1LES,0LES V DD V= NI V564.3=0 51A µ LES_LLPV DD V= NI V564.3=5 A µ I LI tupnI tnerruCwoL LES_KLC,0KLC ,NI_BF,RM 3LES,2LES,1LES,0LES V DD V,V564.3= NI V0=5 -A µ LES_LLPV DD V,V564.3= NI V0=0 51-A µ V HO 1ETON;egatloVhgiHtuptuO 6.2V V LO 1ETON;egatloVwoLtuptuO 5.0V 05htiwdetanimretstuptuO:1ETON Ω Vot ODD ,noitceSnoitamrofnItnemerusaeMretemaraPehtnI.2/ ."tiucriCtseTdaoLtuptuOV3.3"ees ABSOLUTE MAXIMUM R ATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions be- yond those listed in the DC Characteristics or AC Character- istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU I HI tnerruChgiHtupnI 1KLCV DD V= NI V564.3=0 51A µ 1KLCnV DD V= NI V564.3=5 A µ I LI tnerruCwoLtupnI 1KLCV DD V,V564.3= NI V0=5 -A µ 1KLCnV DD V,V564.3= NI V0=0 51-A µ V PP egatloVtupnIkaeP-ot-kaeP 51.03 .1V V RMC ;egatloVtupnIedoMnommoC 2,1ETON 5.0+DNGV DD 58.0-V sadenifedsiegatlovedomnommoC:1ETONV HI . si1KLCn,1KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON V DD .V3.0+ lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU f XAM ycneuqerFtuptuO 526.510 52z HM pt HL ,yaleDnoitagaporP 1ETON;hgiH-ot-woL 0KLC ,V0=LES_LLP f ≤ 2÷xQ,zHM052 57 s n 1KLCn,1KLC ,V0=LES_LLP f ≤ 2÷xQ,zHM052 53 .7s n )Ø(t ;tesffOesahPcitatS 4,2ETON 0KLC ,V3.3=LES_LLP FERf ≤ 1÷xQ,zHM002 001-5 20 51s p 1KLCn,1KLC ,V3.3=LES_LLP FERf ≤ 1÷xQ,zHM761 51-5 31+5 82s p ,V3.3=LES_LLP 1÷xQ,zHM002=FERf 05-0 01+0 52s p 0KLC ,V3.3=LES_LLP 2*xQ,zHM66=FERf 051-5 2-0 01s p 1KLCn,1KLC ,V3.3=LES_LLP 2*xQ,zHM66=FERf 00 510 03s p t )o(ks ;wekStuptuO 4,3ETON 0KLCV 0=LES_LLP5 6s p 1KLCn,1KLCV 0=LES_LLP5 5s p t )cc(tij4 ETON;rettiJelcyC-ot-elcyCf TUO zHM04>5 4s p tL emiTkcoLLLP 1S m tR t/ F emiTllaF/esiRtuptuO 0040 59s p cdoe lcyCytuDtuptuO 347 5% ,zHM54=nif,edom4xLLP zHM081=TUOf 743 5% taderusaemsretemarapllAf XAM .esiwrehtodetonsselnu tatuptuoehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON V ODD .2/ ehtdnakcolcecnerefertupniehtneewtebecnereffidemitehtsadenifeD:2ETON langistupnikcabdeefegareva .elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON VtaderusaeM ODD .2/ .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V DD egatloVylppuSeroC 573.25 .25 26.2V V ADD egatloVylppuSgolanA 573.25 .25 26.2V V ODD egatloVylppuStuptuO 573.25 .25 26.2V I DD tnerruCylppuSrewoP 09A m I ADD tnerruCylppuSgolanA 51A m I ODD tnerruCylppuStuptuO 02A m lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU V HI tupnI egatloVhgiH ,LES_KLC,LES_LLP ,3LES,2LES,1LES,0LES RM,NI_BF 2V DD 3.0+V 0KLC2 V DD 3.0+V V LI tupnI egatloVwoL ,LES_KLC,LES_LLP ,3LES,2LES,1LES,0LES RM,NI_BF 3.0-8 .0V 0KLC3 .0-3 .1V I HI tupnI tnerruChgiH LES_KLC,0KLC ,NI_BF,RM 3LES,2LES,1LES,0LES V DD V= NI V526.2=0 51A µ LES_LLPV DD V= NI V526.2=5 A µ I LI tupnI tnerruCwoL LES_KLC,0KLC ,NI_BF,RM 3LES,2LES,1LES,0LES V DD V,V526.2= NI V0=5 -A µ LES_LLPV DD V,V526.2= NI V0=0 51-A µ V HO 1ETON;egatloVhgiHtuptuO 8.1V V LO 1ETON;egatloVwoLtuptuO 5.0V 05htiwdetanimretstuptuO:1ETON Ω Vot ODD ,noitcesnoitamrofnItnemerusaeMretemaraPehtnI.2/ .erugif"tiucriCtseTdaoLtuptuOV5.2"ees lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU I HI tnerruChgiHtupnI 1KLCV DD V= NI V526.2=0 51A µ 1KLCnV DD V= NI V526.2=5 A µ I LI tnerruCwoLtupnI 1KLCV DD V,V526.2= NI V0=5 -A µ 1KLCnV DD V,V526.2= NI V0=0 51-A µ V PP egatloVtupnIkaeP-ot-kaeP 51.03 .1V V RMC ;egatloVtupnIedoMnommoC 2,1ETON 5.0+DNGV DD 58.0-V sadenifedsiegatlovedomnommoC:1ETONV HI . si1KLCn,1KLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON V DD .V3.0+
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = 0°C TO 70°C lobmySr etemaraPs noitidnoCtseTm uminiMl acipyTm umixaMs tinU f XAM ycneuqerFtuptuO 526.510 52z HM pt HL ,yaleDnoitagaporP 1ETON;hgiH-ot-woL 0KLC ,V0=LES_LLP f ≤ 2÷xQ,zHM052 57 s n 1KLCn,1KLC ,V0=LES_LLP f ≤ 2÷xQ,zHM052 53 .7s n )Ø(t ;tesffOesahPcitatS 4,2ETON 0KLC ,V5.2=LES_LLP FERf ≤ 1÷xQ,zHM002 052-5 20 02s p 1KLCn,1KLC ,V5.2=LES_LLP 1÷xQ,zHM331=FERf 05-0 010 52s p ,V5.2=LES_LLP 1÷xQ,zHM002=FERf 001-0 01+0 03s p 0KLC ,V5.2=LES_LLP 2*xQ,zHM66=FERf 051-5 2-0 01s p 1KLCn,1KLC ,V5.2=LES_LLP 2*xQ,zHM66=FERf 00 510 03s p t )o(ks ;wekStuptuO 4,3ETON 0KLCV 0=LES_LLP5 6s p 1KLCn,1KLCV 0=LES_LLP5 5s p t )cc(tij4 ETON;rettiJelcyC-ot-elcyCf TUO zHM04>5 4s p t (tij θ)5 ,4ETON;rettiJesahP ,V5.2=LES_LLP 2*xQ,zHM66=FERf 05±s p tL emiTkcoLLLP 1S m tR t/ F emiTllaF/esiRtuptuO 0040 59s p cdoe lcyCytuDtuptuO 347 5% ,zHM54=nif,edom4xLLP zHM081=TUOf 545 5% taderusaemsretemarapllAf XAM .esiwrehtodetonsselnu tatuptuoehtottniopgnissorctupnilaitnereffidehtmorfderusaeM:1ETON V ODD .2/ ehtdnakcolcecnerefertupniehtneewtebecnereffidemitehtsadenifeD:2ETON langistupnikcabdeefegareva .elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLPehtnehw .snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuoneewtebwekssadenifeD:3ETON VtaderusaeM ODD .2/ .56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:4ETON .desuecruostupniehtnotnednepedsirettijesahP:5ETON
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR DIFFERENTIAL INPUT LEVEL 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT SCOPE Qx LVCMOS 1.65V±5% -1.165V±5% OUTPUT SKEW CYCLE-TO-CYCLE J ITTER OUTPUT RISE/FALL TIME SCOPE Qx LVCMOS 1.25V±5% -1.25V±5% PARAMETER MEASUREMENT INFORMATION V CMR Cross Points V PP GND CLK nCLK VDD tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Q0:Q7 ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 t sk(o) VDDO VDDO 2Qy Qx Clock Outputs 20% 80% 80% 20% tR tF GND GND VDD, VDDA, VDDO VDD, VDDA, VDDO
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PROPAGATION D ELAYPHASE JITTER & S TATIC PHASE OFFSET Q0:Q7 tPD VDDO ➤ ➤ VDD CLK1 nCLK1 CLK0 tPW tPERIOD VDDO VDDO VDDO tPW tPERIOD odc = Q0:Q7 (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset ➤ ➤t(Ø) VOH VOL VOH VOL VDDO nCLK1 FB_IN tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter CLK1
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Other signals GND VDDA
50 Ohm
FIGURE 4B. PCB B OARD LAYOUT FOR ICS8705 The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted in- ductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. The differential 50 Ω output traces should have same length. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. Make sure no other signal traces are routed between the clock trace pair. The series termination resistors should be located as close to the driver pins as possible.
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7. P ACKAGE DIMENSIONS
TABLE 8. O RDERING INFORMATION the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TEEHSYROTSIHNOISIVER veRe lbaTe gaPe gnahCfonoitpircseDe taD A1 m argaiDkcolBdetadpU 20/52/1 B A3T A5T B5T;F4T:D4T 7,6 nmulocegnaRycneuqerFecnerefeRehtdesiver-elbaTnoitcnuFelbanELLP morfworycneuqerFtuptuOehtdetadpu-elbaTscitsiretcarahCCAV3.3 .xaMzHM572ot.xaMzHM053 .selbatV5.2deddA 20/41/3 C A3T A5T B5T nmulocegnaRycneuqerFecnerefeRehtdesiver-elbaTnoitcnuFelbanELLP morfworycneuqerFtuptuOehtdetadpu-elbaTscitsiretcarahCCAV3.3 .xaMzHM052ot.xaMzHM572 morfworycneuqerFtuptuOehtdetadpu-elbaTscitsiretcarahCCAV5.2 .xaMzHM052ot.xaMzHM572 20/4/4 C1 T2 . snoitpircsedniprewopdesiver-elbaTnoitpircseDniP 20/01/4 C2 T2 C ni)lacipyt(Fp32dda-elbaTscitsiretcarahCniP DP .wor2 0/51/7 C1 T2 ".01nipottcennoC"decalper,noitpircsedmorf01#niP-elbaTnoitpircseDniP ".stuptuoehtfoenoottcennoC"htiw 20/1/8 C1 T 2 .noitpircsedRMdnanoitpircsed0KLCdesiveR .margaiDemiTllaF/esiRtuptuOdesiveR 20/12/8 D D4T,A4T,1T B5T,A5T 6,4,2 7,5 VrofnoitpircseddesiveR DD .ylppusevitisoPmorfylppuseroCdaerot snoitidnoctsettnereffidhtiw"cdo"otworrehtonadedda,scitsiretcarahCCA .seulavdna .tamrofdetadpU 20/22/11 E B5T&A5T 7&5 .noitpircsedRMdesiver-elbatnoitpircseDniP .1KLCn,1KLCrofstimiltesffOesahPcitatSehtdegnahC-selbatCA 30/22/1 F B5T&A5T7 &5 ."2*xQ,zHM66=FERf"htiwtesffOesahPcitatSdedda-selbatCA 4ETONdaerotretemarapOPSniopytdetcerroc-elbatCAV3.3 .7ETONmorf 30/31/2 G B5T7 .5etoNdna,cepsrettiJesahPdedda-elbaTscitsiretcarahCCAV5.2 .margaiDOPS&rettiJesahPhtiwmargaiDtesffOesahPcitatSdecalpeR 30/41/3 G 2T2 Cdegnahc-elbaTscitsiretcarahCniP NI .lacipytFp4ot.xamFp4morf .noitcesecafretnItupnIkcolClaitnereffiDdeddA 30/51/5 G3 1&21e nilediuGtuoyaLdeddA 30/6/6 G6 T4 1r ebmuntrap"eerF-daeL"dedda-elbaTnoitamrofnIgniredrO 40/61/6 G 8T .telluberutarepmetdedda-noitceSserutaeF .eton"eerF-daeL"deddA-elbaTnoitamrofnIgniredrO 50/81/3 H8 T 61 .SCImorfTDIhtiwretoof/redaehs'teehsataddetadpU .nmulocrebmuNredrO/traPmorfxiferp"SCI"devomeR .egaPtcatnoCdeddA 01/2/7
8705BY www.idt.com REV. H JULY 2, 2010 ICS8705 ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR We’ve Got Your Timing Solution. Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 Tech Support netcom@idt.com
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