8705BYILF

8705I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
• PDF pages: 19

Technical content

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEETNot Recommend for New Designs 8705I REVISION E 7/13/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 8705I is a highly versatile 1:8 Differential-to-LVCMOS/ LVTTL Clock Generator. The 8705I has two selectable clock inputs. The CLK1, nCLK1 pair can accept most standard differential input levels. The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The 8705I has a fully integrated PLL and can be confi gured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers.

FEATURES

• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration with confi gurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum) CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature  Not Recommended for New Designs For new designs, contact IDT. BLOCK DIAGRAM P IN ASSIGNMENT 32-Lead LQFP 7mm x 7mm x 1.4 mm Y Package Top View

2 REVISION E 7/13/15

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 SEL0, SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS/LVTTL interface levels. 3 CLK0 Input Pulldown Clock input. LVCMOS/LVTTL interface levels. 5 CLK1 Input Pulldown Non-inverting differential clock input. 6 nCLK1 Input Pullup Inverting differential clock input. LOW, selects LVCMOS CLK0. LVCMOS/LVTTL interface levels.

8 MR Input Pulldown

10 FB_IN Input Pulldown

clocks with “zero delay”. Connect to one of the outputs. LVCMOS/LVTTL interface levels. 11 SEL2 Input Pulldown Determines output divider values in Table 3. LVCMOS/LVTTL interface levels. DDO Power Output supply pins. Output Clock output. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. 14, 18, 22, 26 GND Power Power supply ground. 29 SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS/LVTTL interface levels. 30 V DDA Power Analog supply pin.

31 PLL_SEL Input Pullup

Selects between the PLL and reference clock as input to the dividers. selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

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TABLE 3A. PLL ENABLE FUNCTION TABLE TABLE 3B. PLL BYPASS FUNCTION TABLE Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q0:Q7 0000 ÷ 8 0001 ÷ 8 0010 ÷ 8 0 0 1 1 ÷ 16 0 1 0 0 ÷ 16 0 1 0 1 ÷ 16 0 1 1 0 ÷ 32 0 1 1 1 ÷ 32 1 0 0 0 ÷ 64 1 0 0 1 ÷ 128 1010 ÷ 4 1011 ÷ 4 1100 ÷ 8 1101 ÷ 2 1110 ÷ 4 1111 ÷ 2 Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0:Q7 0 0 0 0 125 - 250 ÷ 1 0 0 0 1 62.5 - 125 ÷ 1 0 0 1 0 31.25 - 62.5 ÷ 1 0 0 1 1 15.625 -31.25 ÷ 1 0 1 0 0 125 - 250 ÷ 2 0 1 0 1 62.5 - 125 ÷ 2 0 1 1 0 31.25 - 62.5 ÷ 2 0 1 1 1 125 - 250 ÷ 4 1 0 0 0 62.5 - 125 ÷ 4 1 0 0 1 125 - 250 ÷ 8 1 0 1 0 62.5 - 125 x 2 1 0 1 1 31.25 - 62.5 x 2 1 1 0 0 15.625 - 31.25 x 2 1 1 0 1 31.25 - 62.5 x 4 1 1 1 0 15.625 - 31.25 x 4 1 1 1 1 15.625 - 31.25 x 8

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEET

4 REVISION E 7/13/15

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 90 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR DD + 0.3 V CLK0 2 V DD + 0.3 V VIL Input Low Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR -0.3 0.8 V CLK0 -0.3 1.3 V I IH Input High Current CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 V DD = VIN = 3.465V 150 µA PLL_SEL V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 V DD = 3.465V, VIN = 0V -5 µA PLL_SEL V DD = 3.465V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 2.6 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section, see “3.3V Output Load Test Circuit” fi gure. ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

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TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 CLK0 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 57 n s CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 5 7.3 ns t(Ø) Static Phase Offset; NOTE 2, 4 CLK0 PLL_SEL = 3.3V, fREF ≤ 200MHz, Qx ÷ 1 -100 25 150 ps CLK1, nCLK1 PLL_SEL = 3.3V, fREF ≤ 167MHz, Qx ÷ 1 -15 +135 285 ps PLL_SEL = 3.3V, fREF = 200MHz, Qx ÷ 1 -50 +100 250 ps tsk(o) Output Skew; NOTE 3, 4 CLK0 PLL_SEL = 0V 65 ps CLK1, nCLK1 PLL_SEL = 0V 55 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 45 ps tL PLL Lock Time 1m S tR Output Rise Time 400 950 ps tF Output Fall Time 400 950 ps odc Output Duty Cycle 43 57 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defi ned as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO/2. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK1 V DD = VIN = 3.465V 150 µA nCLK1 V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK1 V DD = 3.465V, VIN = 0V -5 µA nCLK1 V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD - 0.85 V NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEET

6 REVISION E 7/13/15

TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 90 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR DD + 0.3 V CLK0 2 V DD + 0.3 V VIL Input Low Voltage PLL_SEL, CLK_SEL, SEL0, SEL1, SEL2, SEL3, FB_IN, MR -0.3 0.8 V CLK0 -0.3 1.3 V I IH Input High Current CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 V DD = VIN = 2.625V 150 µA PLL_SEL V DD = VIN = 2.625V 5 µA IIL Input Low Current CLK0, CLK_SEL MR, FB_IN, SEL0, SEL1, SEL2, SEL3 V DD = 2.625V, VIN = 0V -5 µA PLL_SEL V DD = 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 1.8 V VOL Output Low Voltage; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information section, see “2.5V Output Load Test Circuit” fi gure. Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK1 V DD = VIN = 2.625V 150 µA nCLK1 V DD = VIN = 2.625V 5 µA IIL Input Low Current CLK1 V DD = 2.625V, VIN = 0V -5 µA nCLK1 V DD = 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD - 0.85 V NOTE 1: Common mode voltage is defi ned as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V.

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TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 CLK0 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 57 n s CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 5 7.3 ns t(Ø) Static Phase Offset; NOTE 2, 4 CLK0 PLL_SEL = 2.5V, fREF ≤ 200MHz, Qx ÷ 1 -250 25 200 ps CLK1, nCLK1 PLL_SEL = 2.5V, fREF = 133MHz, Qx ÷ 1 -50 100 250 ps PLL_SEL = 2.5V, fREF = 200MHz, Qx ÷ 1 -100 +100 300 ps tsk(o) Output Skew; NOTE 3, 4 CLK0 PLL_SEL = 0V 65 ps CLK1, nCLK1 PLL_SEL = 0V 55 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 45 ps tjit(q) Phase Jitter; NOTE 4, 5 PLL_SEL = 2.5V, fREF = 66MHz, Qx * 2 ±50 ps tL PLL Lock Time 1m S tR Output Rise Time 400 950 ps tF Output Fall Time 400 950 ps odc Output Duty Cycle 43 57 % All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defi ned as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. Measured at V DDO/2. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used.

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEET

8 REVISION E 7/13/15

2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW CYCLE-TO-CYCLE JITTER OUTPUT RISE/FALL TIME PARAMETER MEASUREMENT INFORMATION

9 Zero Delay, Differential-to-LVCMOS/

tPW, odc AND tPERIOD PROPAGATION DELAYPHASE JITTER & STATIC PHASE OFFSET (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) t(Ø) mean = Static Phase Offset tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEET

10 REVISION E 7/13/15

APPLICATION INFORMATION

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT FIGURE 1. POWER SUPPLY FILTERING

11 Zero Delay, Differential-to-LVCMOS/

FIGURE 3C. CLK/nCLK I NPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3B. CLK/nCLK I NPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/nCLK I NPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for theCLK/nCLK input driven by the most common driver types. The input interfaces suggested here are FIGURE 3A. CLK/nCLK I NPUT DRIVEN BY LVHSTL D RIVER examples only. Please consult with the vendor of the driver component to confi rm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator 8705I DATA SHEET

12 REVISION E 7/13/15

0.1uF VDD VDD Zo = 50 VDD 10 - 15 VDD R2 43 RD1 Not Install (U1-24) (U1-32) Logic Input Pin Examples 0.1uF SEL2 0.1uF To Logic Input pins (U1-9) VDD ICS8705 SEL0 SEL1 CLK0 nc CLK1 nCLK1 CLK_SEL MR VDD FB_IN SEL2 VDDO GND VDDO GND VDDO GND VDDO VDD PLL_SEL VDDA SEL3 VDDO GND VDD=3.3V or 2.5V To Logic Input pins R4 43 VDD C16 10u PLL_SEL R1 43 0.1uF Zo = 50 Zo = 50 SEL3 SEL1 RU2 Not Install VDDA 0.1uF Ro ~ 7 Ohm Driv er_LVCMOS (U1-20) SEL0 0.1uF Set Logic Input to '1' RU1 Set Logic Input to '0' 0.1uF RD2 C11 0.01u LAYOUT GUIDELINE The schematic of the 8705I layout example is shown in Figure 4A. The 8705I recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P .C. board. FIGURE 4A. 8705I LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE

13 Zero Delay, Differential-to-LVCMOS/

FIGURE 4B. PCB BOARD LAYOUT FOR 8705I The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the pow- er pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC fi lter consisting of R7, C11, and C16 should be placed as close to the V DDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed fi rst and should be locked prior to routing other signal traces.

• The differential 50 Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines.
• Keep the clock traces on the same layer. Whenever pos- sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the clock trace pair.
• The series termination resistors should be located as close to the driver pins as possible.

14 REVISION E 7/13/15

TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

15 Zero Delay, Differential-to-LVCMOS/

TABLE 7. PACKAGE DIMENSIONS

16 REVISION E 7/13/15

TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

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Rev Table Page Description of Change Date B PLL Enable Function Table - revised the Reference Frequency Range column 3.3V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. 2.5V AC Characteristics Table - updated the Output Frequency row from 275MHz Max. to 250MHz Max. 4/5/02 B 1 2 Pin Description Table - revised power pin descriptions. 4/10/02 B 22 Pin Characteristics Table - added 23pF to CPD row. 7/15/02 B1 2 Pin Description Table - Pin# 10 from description, replaced “Connect to pin 10.” with “Connect to one of the outputs.” 8/1/02 B1 2 Revised CLK0 description and MR description. Revised Output Rise/Fall Time Diagram. 8/21/02 C 4A & 4D 5A & 5B 4 & 6 5 & 7 Pin Description table - revised MR and VDD descriptions. Power Supply Table - changed VDD parameter to correspond with the pin de- scription. AC tables - Changed the Static Phase Offset limits for CLK1, nCLK1. 1/22/03 D T5B 7 2.5V AC Characteristics Table - added Phase Jitter spec, and Note 5. Replaced Static Phase Offset Diagram with Phase Jitter & SPO Diagram. 3/14/03 D T2 2 12 & 13 Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. ROUT, added 5W min. and 12W max. Added Differential Clock Input Interface section. Added Layout Guideline and PCB Board Layout. 7/14/03 D T8 Added Lead-Free bullet to Features section. Added Lead-Free part number to Ordering Information table. 7/8/04 E T8 16 Updated datasheet’s header/footer with IDT from ICS. Removed “”ICS”” prefi x from Part/Order Number column. Corrected packaging column Added Contact Page. 7/16/10 E 1 NRND - Nor Recommended For New Designs 5/30/13 Updated data sheet format 7/13/15

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San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifi cations described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifi cations and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth- er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason- ably expected to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2015. All rights reserved.

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