87021I

87021I RENESAS | Alldatasheet

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• Manufacturer or author: rdvorak
• PDF pages: 14

Technical content

÷1/÷2 Differential-to-LVCMOS/LVTTL Clock Generator 87021I Data Sheet ©2grated Device Technology, Inc September 2, 20211 GENERAL DESCRIPTION The 87021I is a high performance ÷1/÷2 Differential-to-LVCMOS/ LVTTL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. Guaranteed part- to-part skew characteristics make the 87021I ideal for those clock distribution applications demanding well defi ned performance and repeatability.

FEATURES

 Two single-ended LVCMOS/LVTTL outputs One differential CLK, nCLK input pair  CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  Maximum output frequency: 250MHz  Additive phase jitter, RMS: 0.18ps (typical)  Output skew: 50ps (maximum)  Part-to-part skew: 450ps (maximum)  Propagation delay: 3.4ns (maximum)  Full 3.3V or 2.5V operating supply  -40°C to 85°C ambient operating temperature  Availalbe in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT 87021I 8-Lead SOIC 3.90mm x 4.90mm x 1.375mm package body M Package Top View CLK nCLK MR F_SEL VDD GND CLK nCLK MR F_SEL ÷2R

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1 CLK Input Pulldown Non-inverting differential clock input. 2 nCLK Input Pullup Inverting differential clock input.

3 MR Input Pulldown

4 F_SEL Input Pulldown Selects divider value for Qx outputs as described in Table 3. LVCMOS / LVTTL interface levels. 5 GND Power Power supply ground. 6 Q1 Output Singled-ended output. LVCMOS/LVTTL interface levels. 7 Q0 Output Singled-ended output. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 3. FUNCTION TABLE FIGURE 1. TIMING DIAGRAM

1 X Reset: Q0, Q1 outputs low

©2016 Integrated Device Technology, Inc September 2, 20214 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DD + 0.5V Package Thermal Impedance, θ JA 103°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 3.135 3.3 3.465 V I DD Power Supply Current 60 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.3 V DD + 0.3 V V IL Input Low Voltage -0.3 0.7 V I IH Input High Current V DD = V IN = 3.465V 150 µA I IL Input Low Current V DD = 3.465V, V IN = 0V -5 µA V OH Output High Voltage; NOTE 1 V DD = 3.465V 2.6 V V OL Output Low Voltage; NOTE 1 V DD = 3.465V or 2.625V 0.5 V NOTE 1: Outputs terminated with 50Ω to V DD /2. See Parameter Measurement Information section, “3.3V Output Load Test Circuit” diagram. TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 2.375 2.5 2.625 V I DD Power Supply Current 35 mA TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V IH Input High Voltage 1.1 V DD + 0.3 V V IL Input Low Voltage -0.3 0.5 V I IH Input High Current V DD = V IN = 2.625V 150 µA I IL Input Low Current V DD = 2.625V, V IN = 0V -5 µA V OH Output High Voltage; NOTE 1 V DD = 2.625V 1.8 V V OL Output Low Voltage; NOTE 1 V DD = 2.625V 0.5 V NOTE 1: Outputs terminated with 50Ω to V DD /2. See Parameter Measurement Information section, “2.5V Output Load Test Circuit” diagram.

©2016 Integrated Device Technology, Inc September 2, 20215 TABLE 5A. AC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz t PD Propagation Delay; NOTE 1 CLK to Qx 2.1 3.4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sec- tion 250MHz, Integration Range: 12kHz – 20MHz 0.18 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 450 ps tsk(o) Output Skew; NOTE 3, 4 50 ps t R / t F Output Rise/Fall Time 20% to 80% 250 700 ps odc Output Duty Cycle; Fout ≤ 133MHz 45 55 % NOTE 5 Fout > 133MHz 40 60 % NOTE 1: Measured from the differential input crossing point to the output at V DD /2. NOTE 2: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DD /2. NOTE 3: This parameter is defi ned in accordance with JEDEC Standard 65. NOTE 4: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. NOTE 5: Output Duty Cycle assuming 50% input duty cycle. TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, V DD = 3.3V±5% OR V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current CLK V DD = V IN = 3.465V or 2.625V 150 µA nCLK V DD = V IN = 3.465V or 2.625V 5 µA I IL Input Low Current CLK V DD = 3.465V or 2.625V, V IN = 0V -5 µA nCLK V DD = 3.465V or 2.625V, V IN = 0V -150 µA V PP Peak-to-Peak Input Voltage 0.15 1.3 V V CMR Common Mode Input Voltage; NOTE 1 GND + 0.5 V DD - 0.85 V NOTE 1: Common mode voltage is defi ned as V IH TABLE 5B. AC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units f MAX Output Frequency 250 MHz t PD Propagation Delay; NOTE 1 CLK to Qx 2.7 3.4 ns tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sec- tion 250MHz, Integration Range: 12kHz – 20MHz 0.3 ps tsk(pp) Part-to-Part Skew; NOTE 2, 3 450 ps tsk(o) Output Skew; NOTE 3, 4 25 ps t R / t F Output Rise/Fall Time 20% to 80% 250 700 ps odc Output Duty Cycle; Fout ≤ 133MHz 45 55 % NOTE 5 Fout > 133MHz 40 60 % For NOTES, please see above Table 5A.

©2016 Integrated Device Technology, Inc September 2, 20216 ADDITIVE PHASE JITTER Additive Phase Jitter @ 250MHz (12kHz to 20MHz) = 0.18ps typical The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

©2016 Integrated Device Technology, Inc September 2, 20217 PARAMETER MEASUREMENT INFORMATION PROPAGATION DELAY 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW DIFFERENTIAL INPUT LEVEL 2.5V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

TABLE 6. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc September 2, 202113 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T2 2 Pin Characteristics Table - added R OUT row. 8/26/08 B T8 Removed ICS from the part numbers where needed. General Description - Removed the ICS chip and HiPerClockS. Features Section - Removed reference to lead free packages. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Updated header and footer. 1-26-16 B 8 12 Changed Shipping Packaging from "Tray" to "Tube". 9-2-2021

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