8701I RENESAS | Alldatasheet

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Low Skew, ÷1, ÷2 Clock Generator 8701I Data Sheet ©2016 Integrated Device Technology, Inc Revision C January 22, 20161 GENERAL DESCRIPTION The 8701I is a low skew, ÷1, ÷2 Clock Generator. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable in- puts, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The 8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the 8701I ideal for those clock distribution applications demanding well defi ned performance and repeatability.

FEATURES

 Twenty LVCMOS outputs, 7Ω typical output impedance  LVCMOS / LVTTL clock input  Maximum input frequency: 250MHz  Bank enable logic allows unused banks to be disabled in reduced fanout applications  Bank skew: 200ps  Output skew: 250ps  Multiple frequency skew: 300ps  Part-to-part skew: 600ps  3.3V or mixed 3.3V input, 2.5V output operating supply  -40°C to 85°C ambient operating temperature  Other divide values available on request  Available in lead-free RoHS compliant package BLOCK DIAGRAM P IN ASSIGNMENT 48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View

TABLE 1. PIN DESCRIPTIONS VDDO Power Output supply pins. GND Power Power supply ground. 16, 20 V DD Power Positive supply pins. QA3, QA4 Output Bank A outputs.LVCMOS / LVTTLinterface levels. 7Ω typical output impedance. QB3, QB4 Output Bank B outputs.LVCMOS / LVTTLinterface levels. 7Ω typical output impedance. QC3, QC4 Output Bank C outputs.LVCMOS / LVTTLinterface levels. 7Ω typical output impedance. QD3, QD4 Output Bank D outputs. LVCMOS / LVTTLinterface levels. 7Ω typical output impedance. 22 CLK Input Pulldown LVCMOS / LVTTL clock input. 13 DIV_SELD Input Pullup Controls frequency division for Bank D outputs. LVCMOS / LVTTLinterface levels. 14 DIV_SELC Input Pullup Controls frequency division for Bank C outputs. LVCMOS / LVTTLinterface levels. 23 DIV_SELB Input Pullup Controls frequency division for Bank B outputs. LVCMOS / LVTTLinterface levels. 24 DIV_SELA Input Pullup Controls frequency division for Bank A outputs. LVCMOS / LVTTLinterface levels. BANK_EN0 Input Pullup Enables and disables outputs by banks. LVCMOS / LVTTLinterface levels. enabled. Whe LOW, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTLinterface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS TABLE 3. FUNCTION TABLE

0 X X X Hi Z Hi Z Hi Z Hi Z zero

©2016 Integrated Device Technology, Inc Revision C January 22, 20164 TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V IDD Power Supply Current 100 mA ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

©2016 Integrated Device Technology, Inc Revision C January 22, 20165 TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE DD + 0.3 V CLK 2 V DD + 0.3 V VIL Input Low Voltage DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE -0.3 0.8 V CLK -0.3 1.3 V I IH Input High Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE V DD = VIN = 3.465V 5 µA CLK V DD = VIN = 3.465V 150 µA IIL Input Low Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE V DD = 3.465V, VIN = 0V -150 µA CLK V DD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage VDD = VDDO = 3.135V IOH = -36mA 2.6 V VDD = 3.135V, VDDO = 2.375 IOH = -27mA 1.8 V VOL Output Low Voltage VDD = VDDO = 3.135V IOL = 36mA 0.5 V VDD = 3.135V, VDDO = 2.375 IOL = 27mA 0.5 V

©2016 Integrated Device Technology, Inc Revision C January 22, 20166 TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Input Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 0MHz ≤ f ≤ 200MHz 2.2 3.6 ns tpHL Propagation Delay, High-to-Low; NOTE 1 0MHz ≤ f ≤ 200MHz 2.2 3.6 ns tsk(b) Bank Skew; NOTE 2, 7 Measured on rising edge at VDDO/2 200 ps tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at VDDO/2 250 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDO/2 300 ps tsk(pp) Part to Part Skew; NOTE 5, 7 Measured on rising edge at VDDO/2 600 ps tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% 200 900 ps tPW Output Pulse Width 0MHz ≤ f ≤ 200MHz tCYCLE/2 - 0.6 tCYCLE/2 tCYCLE/2 + 0.6 ns f = 200MHz 1.9 2.5 3.1 ns tEN Output Enable Time; NOTE 6 f = 10MHz 6 ns tDIS Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD input crossing point to the output at VDDO/2. NOTE 2: Defi ned as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4 Defi ned as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision C January 22, 20167 TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Input Frequency 250 MHz tpLH Propagation Delay, Low-to-High; NOTE 1 0MHz ≤ f ≤ 200MHz 2.4 3.7 ns tpHL Propagation Delay, High-to-Low; NOTE 1 0MHz ≤ f ≤ 200MHz 2.4 3.7 ns tsk(b) Bank Skew; NOTE 2, 7 Measured on rising edge at VDDO/2 225 ps tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at VDDO/2 250 ps tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDO/2 300 ps tsk(pp) Part to Part Skew; NOTE 5, 7 Measured on rising edge at VDDO/2 650 ps tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% 200 900 ps tPW Output Pulse Width 0MHz ≤ f ≤ 200MHz tCYCLE/2 - 0.6 tCYCLE/2 tCYCLE/2 + 0.6 ns f = 200MHz 1.9 2.5 3.1 ns tEN Output Enable Time; NOTE 6 f = 10MHz 6 ns tDIS Output Disable Time; NOTE 6 f = 10MHz 6 ns All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD input crossing point to the output at VDDO/2. NOTE 2: Defi ned as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4 Defi ned as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defi ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V DDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision C January 22, 20168 PARAMETER MEASUREMENT INFORMATION OUTPUT SKEW 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD OUTPUT RISE/FALL TIME BANK SKEW (where X denotes outputs in the same bank) PROPAGATION DELAY

©2016 Integrated Device Technology, Inc Revision C January 22, 20169 POWER CONSIDERATIONS For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer. Driver Termination For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination.

APPLICATION INFORMATION

INPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left fl oating. We recommend that there is no trace attached.

TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 7. PACKAGE DIMENSIONS

TABLE 7. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision C January 22, 201613 REVISION HISTORY SHEET Rev Table Page Description of Change Date A 8 - 10 Updated format throughout the datasheet. Renamed LVCMOS_CLK to CLK. Renamed V DDI to VDD. Pin Description Table, revised nMR/OE description. 3.3V AC Characteristics Table, updated notes. 3.3V/2.5V Characteristics Table, updated notes. Updated drawings. Added Power Consideration and Driver Termination notes. Added Reliability Information and Transistor Count. Revised Package Outline. 8/19/02 B Features Section - added lead-free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Parameter Measurement Information - added Bank Skew diagram. Application Information - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking and note. Updated format throughout the data sheet. 2/28/06 CT 7 1 2 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/27/10 CT 7 Removed ICS from the part number where needed. Features Section - removed reference to leaded package. Ordering Information - removed quantity for tape and reel. Deleted LF note below the table. Updated header and footer. 1/22/16

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