87016I

87016I RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Renesas Electronics Corporation
• PDF pages: 16

Technical content

Features

• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1/CLK1 or LVCMOS/LVTTL clock input
• CLK1, CLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 50ps (maximum
• Part-to-Part Skew: 800ps (maximum)
• Supply modes: Core/Output 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Lead-free packaging Block Diagram Pin Assignment 87016I 48-LQFP 7 × 7 × 1.4 mm package body Y Package Top View MR/OE CLK0 CLK1 CLK1 CLK_SEL DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END QA0:QA3 QB0:QB3 QC0:QC3 QD0:QD3 LE LE LE LE D D D D 13 14 15 16 17 18 19 20 21 22 23 24 VDD CLK0 DIV_SELA DIV_SELB DIV_SELC DIV_SELD CLK_ENA CLK_ENB CLK_ENC CLK_END MR/OE GND GND QB0 VDDOB QB1 GND QB2 VDDOB QB3 GND QC0 VDDOC QC1 QD3 VDDOD QD2 GND QD1 VDDOD QD0 GND QC3 VDDOC QC2 GND CLK1 CLK1 CLK_SEL GND QA0 VDDOA QA1 GND QA2 VDDOA QA3 VDD 48 47 46 45 44 43 42 41 40 39 38 37

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 1, 48 V DD Power Positive supply pins. 2 CLK0 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interf ace levels. 3 DIV_SELA Input Pullup Controls frequency division for Bank A outputs. See Table 3. LVCMOS / LVTTL interface levels. 4 DIV_SELB Input Pullup Controls frequency division for Bank B outputs. See Table 3. LVCMOS / LVTTL interface levels. 5 DIV_SELC Input Pullup Controls frequency division for Bank C outputs. See Table 3. LVCMOS / LVTTL interface levels. 6 DIV_SELD Input Pullup Controls frequency division for Bank D outputs. See Table 3. LVCMOS / LVTTL interface levels. low. LVCMOS/LVTTL interface levels. See Table 3. low. LVCMOS/LVTTL interface levels. See Table 3. low. LVCMOS/LVTTL interface levels. See Table 3. low. LVCMOS/LVTTL interface levels. See Table 3. high impedance. LVCMOS / LVTTL interface levels. QD1, QD0 Output Bank D single-ended clock outputs. LVCMOS/LVTTL interface levels. 14, 18 V DDOD Power Bank D output supply pins. QC1, QC0 Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels. 22, 26 V DDOC Power Bank C output supply pins. QB1, QB0 Output Bank C single-ended clock outputs. LVCMOS/LVTTL interface levels. 30, 34 V DDOB Power Bank B output supply pins. QA1, QA0 Output Bank A single-ended clock ou tputs. LVCMOS/LVTTL interface levels. 38, 42 V DDOA Power Bank B output supply pins. 45 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1, CLK1 inputs. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 46 CLK1 Input Pullup Inverting differential clock input. 47 CLK1 Input Pulldown Non-invert ing differential clock input.

Table 2. Pin Characteristics NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD. Table 3. Function Table

111 A c t i v e f I N

January 22, 2020 4 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, VDDOx = 2.5V ± 5%, 1.8V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD Ox+ 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDOA, VDDOB, VDDOC, VDDOD Output Supply Voltage 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 100 mA IDDOA, IDDOB, IDDOC, IDDOD Output Supply Current 15 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V VDDOA, VDDOB, VDDOC, VDDOD Output Supply Voltage 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 95 mA IDDOA, IDDOB, IDDOC, IDDOD Output Supply Current 8m A

January 22, 2020 5 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Table 4C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C NOTE 1: Outputs terminated with 50 to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit diagrams. Table 4D. Differential DC Characteristics, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single-ended applications, the maximum input voltage for CLK1, CLK1 is VDD + 0.3V. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.465V 2 V DD + 0.3 V VDD = 2.625V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.465V -0.3 0.8 V VDD = 2.625V -0.3 0.7 V IIH Input High Current CLK0, CLK_SEL V DD = VIN = 3.465V or 2.625V 150 µA CLK_EN[A:D], DIV_SEL[A:D], MR/OE VDD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current CLK0, CLK_SEL V DD = 3.465V or 2.625V, VIN = 0V -5 µA CLK_EN[A:D], DIV_SEL[A:D], MR/OE VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDOx = 3.3V ± 5% 2.6 V VDDOx = 2.5V ± 5% 1.8 V VDDOx = 1.8V ± 5%; IOH = -2mA VDDOx – 0.45 V VOL Output Low Voltage; NOTE 1 VDDOx = 3.3V ± 5% 0.5 V VDDOx = 2.5V ± 5% 0.5 V VDDOx = 1.8V ± 5%; IOH = 2mA 0.45 V IOZL Output Hi-Z Current Low -5 µA IOZH Output Hi-Z Current High 5µ A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK1 VDD = VIN = 3.465V or 2.625V 5 µA CLK1 V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK1 VDD = 3.465V or 2.625V, VIN = 0V -150 µA CLK1 V DD = 3.465V or 2.625V, VIN = 0V -5 µA VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

January 22, 2020 6 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Table 5A. AC Characteristics, VDD = VDDOx = 3.3V ± 5%, TA = -40°C to 85°C All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDOx = 2.5V ± 5%, TA = -40°C to 85°C For NOTES, please see above, Table 5A. Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 2.8 3.4 3.9 ns CLK1/CLK1; NOTE 1B 2.75 3.4 4.1 ns tsk(b) Bank Skew; NOTE 2, 6 Me asured on the Rising Edge 50 ps tsk(o) Output Skew; NOTE 3, 6 Me asured on the Rising Edge 170 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle ƒ < 175MHz 45 55 % ƒ  175MHz 40 60 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns Parameter Symbol Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 2.9 3.8 4.7 ns CLK1/CLK1; NOTE 1B 3.0 3.6 4.3 ns tsk(b) Bank Skew; NOTE 2, 6 Me asured on the Rising Edge 70 ps tsk(o) Output Skew; NOTE 3, 6 Me asured on the Rising Edge 210 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 150 700 ps odc Output Duty Cycle ƒ  125MHz 40 60 % tpw Output Pulse Width ƒ > 125MHz t Period/2 – 800 tPeriod/2 + 800 ps tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns

January 22, 2020 7 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Table 5C. AC Characteristics, VDD = 3.3V ± 5%, VDDOx = 2.5V ± 5%, TA = -40°C to 85°C All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Table 5D. AC Characteristics, VDD = 3.3V ± 5%, VDDOx = 1.8V ± 5%, TA = -40°C to 85°C For NOTES, please see above, Table 5C. Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 2.9 3.5 4.0 ns CLK1/CLK1; NOTE 1B 3.0 3.5 4.0 ns tsk(b) Bank Skew; NOTE 2, 6 Meas ured on the Rising Edge 50 ps tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 170 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle ƒ < 175MHz 45 55 % ƒ  175MHz 40 60 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 3.0 3.9 4.7 ns CLK1/CLK1; NOTE 1B 3.0 3.9 4.7 ns tsk(b) Bank Skew; NOTE 2, 6 Meas ured on the Rising Edge 50 ps tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 170 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 200 700 ps odc Output Duty Cycle ƒ < 175MHz 45 55 % ƒ  175MHz 40 60 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns

January 22, 2020 8 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Table 5E. AC Characteristics, VDD = 2.5V ± 5%, VDDOx = 1.8V ± 5%, TA = -40°C to 85°C All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defined as skew within a bank with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOX/2. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. Parameter Symbol Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 3.1 4.1 5.2 ns CLK1/CLK1; NOTE 1B 3.0 3.9 4.7 ns tsk(b) Bank Skew; NOTE 2, 6 Meas ured on the Rising Edge 70 ps tsk(o) Output Skew; NOTE 3, 6 Measured on the Rising Edge 210 ps tsk(pp) Part-to-Part Skew; NOTE 4, 6 800 ps tR / tF Output Rise/Fall Time; NOTE 5 20% to 80% 150 700 ps odc Output Duty Cycle ƒ < 175MHz 45 55 % ƒ  175MHz 40 60 % tEN Output Enable Time; NOTE 5 10 ns tDIS Output Disable Time; NOTE 5 10 ns

January 22, 2020 9 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Parameter Measurement Information 3.3V Core/3.3V LVCMOS Output Load Test Circuit 3.3V Core/2.5V LVCMOS Output Load Test Circuit 2.5V Core/1.8V LVCMOS Output Load Test Circuit 2.5V Core/2.5V LVCMOS Output Load Test Circuit 3.3V Core/1.8V LVCMOS Output Load Test Circuit Differential Input Level SCOPE Qx GND VDD, 1.65V±5% -1.65V±5% VDDO SCOPE Qx GND VDDO VDD 1.25V±5% -1.25V±5% 2.05V±5% SCOPE Qx GND VDDO VDD 0.9V±5% 1.6V±0.9V -0.9V±5% SCOPE Qx GND VDD, 1.25V±5% -1.25V±5% VDDO SCOPE Qx GND VDD VDDO 0.9V±5% 2.4V±0.9V -0.9V±5% VDD GND V CMR Cross Points V PP CLK1 CLK1

January 22, 2020 10 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Parameter Measurement Information, continued Output Skew Propagation Delay Output Rise/Fall Time Part-to-Part Skew Output Duty Cycle/Pulse Width/Period t sk(o) VDDx VDDx Qx Qy tpLH VDDO VDD CLK1 CLK1 QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3 CLK0 Clock Outputs 20% 80% 80% 20% tR tF t sk(pp) VDDOX VDDOX Part 1 Part 2 Qx Qy Part 1 Part 2 tPERIOD tPW tPERIOD odc = VCCOx x 100% tPW QA0:QA3, QB0:QB3, QC0:QC3, QD0:QD3

January 22, 2020 13 LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR 87016I DATASHEET Reliability Information Table 6. JA vs. Air Flow Table for a 48-LQFP NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs. the most current data available.

Ordering Information

Table 8. Ordering Information

Revision History

JA vs. Air Flow Linear Feet per Minute 02 0 0 5 0 0 Single-Layer PCB, JEDEC Standard Test Boards 67.8° C/W 55.9°C/W 50. 1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/ W 42.1°C/W 39.4 °C/W Part/Order Number Marking Package Shipping Packaging Temperature ICS87016AYILF ICS87016AYIL “Lead-Free” 48 Lead LQFP Tray -40 C to 85C ICS87016AYILFT ICS87016AYIL “Lead-F ree” 48 Lead LQFP Tape & Reel -4 0C to 85C Date Description of Change January 22, 2020 • Updated package outline drawings section; added link.

• Updated logos and footer information. March 23, 2015 Ordering Informa tion - updated part marking. Updated datasheet format. March 28, 2013 Corrected typo, VOH: V DD – 0.45 to VDDOx – 0.45 November 15, 2012 Remove leaded par ts from Ordering Information table. May 25, 2007 2.5V AC Charac teristics Table - changed Output Duty Cycle test condition and limits. Added Output Pulse Width. March 30, 2007 Added 2.5V Power Supply DC Characteristics Table. LVCMOS DC Characteristics Table - added 2.5V to VIH/VIL. Differential DC Characteristics Table - added 2.5V to IIH/IIL. Added 2.5V Power Supply DC Characteristics Table. Added 2.5V/1.8V Power Supply DC Characteristics Table. Parameter Measurement Information - added 2.5V Core/2.5V Output Load Test Circuit and 2.5V Core/1.8V Output Load Test Circuit diagrams. Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free Order/Part Number.

© Renesas Electronics Corporation

© Renesas Electronics Corporation Package Revision HistoryRev No.Date CreatedDescription 00Jan 21, 2020Initial release

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