87016AYLFT

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Low Skew, 1-to-16 LVCMOS/LVTTL Clock Generator 87016 DATASHEET 87016 REVISION C 06/26/15 1 ©2015 Integrated Device Technology, Inc. GENERAL DESCRIPTION The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator. The device has 4 banks of 4 outputs and each bank can be independently selected for ÷1 or ÷2 frequency operation. Each bank also has its own power supply pins so that the banks can operate at the following different voltage levels: 3.3V, 2.5V, and 1.8V. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The divide select inputs, DIV_SELA:DIV_SELD, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The bank enable inputs, CLK_ENA:CLK_END, support enabling and disabling each bank of outputs individually. The CLK_ENA:CLK_END circuitry has a synchronizer to prevent runt pulses when enabling or disabling the clock outputs. The master reset input, nMR/OE, resets the ÷1/÷2 fl ip fl ops and also controls the active and high impedance states of all outputs. This pin has an internal pull-up resistor and is normally used only for test purposes or in systems which use low power modes. The 87016 is characterized to operate with the core at bank, output, and part-to-part skew characteristics make the 87016 ideal for those clock applications demanding well-defi ned performance and repeatability.

FEATURES

• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or LVCMOS clock input  CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 30ps (maximum)
• Part-to-part skew: 750ps (maximum)
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package BLOCK DIAGRAM P IN ASSIGNMENT 48-Pin LQFP 7mm x 7mm x 1.4mm body package Y Package Top View

87016 DATA SHEET

2 REVISION C 06/26/15

TABLE 1. PIN DESCRIPTIONS 1, 48 V DD Power Positive supply pins. 2 CLK0 Input Pulldown LVCMOS / LVTTL clock input. 3 DIV_SELA Input Pullup Controls frequency division for Bank A outputs. LVCMOS / LVTTL interface levels.

4 DIV_SELB Input Pullup Controls frequency division for Bank B outputs

LVCMOS / LVTTL interface levels.. 5 DIV_SELC Input Pullup Controls frequency division for Bank C outputs. LVCMOS / LVTTL interface levels. 6 DIV_SELD Input Pullup Controls frequency division for Bank D outputs. LVCMOS / LVTTL interface levels. 7 CLK_ENA Input Pullup Output enable for Bank A outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. 8 CLK_ENB Input Pullup Output enable for Bank B outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. 9 CLK_ENC Input Pullup Output enable for Bank C outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. 10 CLK_END Input Pullup Output enable for Bank D outputs. Active HIGH. If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels. outputs to high impedance. LVCMOS / LVTTL interface levels. 32, 36, 40, 44 GND Power Power supply ground. QD1, QD0 Output Bank D outputs. LVCMOS / LVTTL interface levels. 14, 18 V DDOD Power Output Bank D power supply pins. QC1, QC0 Output Bank C outputs. LVCMOS / LVTTL interface levels. 22, 26 V DDOC Power Output Bank C power supply pins. QB1, QB0 Output Bank B outputs. LVCMOS / LVTTL interface levels. 30, 34 V DDOB Power Output Bank B power supply pins. QA1, QA0 Output Bank A outputs. LVCMOS / LVTTL interface levels. 38, 42 V DDOA Power Output Bank A power supply pins. 45 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels. 46 nCLK1 Input Pullup Inverting differential clock input. 47 CLK1 Input Pulldown Non-inverting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

3 LOW SKEW, 1-TO-16

TABLE 2. PIN CHARACTERISTICS TABLE 3. FUNCTION TABLE

0 X X Hi Z N/A

NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD.

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

4 REVISION C 06/26/15

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V VDDOx Output Supply Voltage; NOTE 1 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.71 1.8 1.89 V IDD Power Supply Current 100 mA IDDOx Output Supply Current; NOTE 2 15 mA NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, and VDDOD. NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, and IDDOD. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL DD + 0.3 V CLK0 2V DD + 0.3 V VIL Input Low Voltage DIV_SELA:DIV_SELD, CLK_ENA:CLK_END, nMR/OE, CLK_SEL -0.3 0.8 V CLK0 -0.3 1.3 V I IH Input High Current CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE V DD = VIN = 3.465V 5 µA CLK0, CLK_SEL VDD = VIN = 3.465V 150 µA IIL Input Low Current CLK_ENA:CLK_END, DIV_SELA:DIV_SELD, nMR/OE V DD = 3.465V, VIN = 0V -150 µA CLK0, CLK_SEL VDD = 3.465V, VIN = 0V -5 µA VOH Output High Voltage; NOTE 1 VDDOx = 3.3V ± 5%; NOTE 2 2.6 V VDDOx = 2.5V ± 5%; NOTE 2 1.8 V VDDOx = 1.8V ± 5%; NOTE 2 IOH = -2mA VDDOx DD - 0.45 V VOL Output Low Voltage; NOTE 1 VDDOx = 3.3V ± 5%; NOTE 2 0.5 V VDDOx = 2.5V ± 5%; NOTE 2 0.5 V VDDOx = 1.8V ± 5%; NOTE 2 IOL = 2mA 0.45 V IOZL Output Tristate Current Low -5 µA IOZH Output Tristate Current High 5µ A NOTE 1: Outputs terminated with 50W to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit. NOTE 2: VDDOx denotes VDDOA, VDDOB, VDDOC and VDDOD. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5 V Outputs, V O -0.5V to V DDOx + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Charac- teristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

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LVCMOS/LVTTL CLOCK GENERATOR TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current nCLK1 V IN = VDD = 3.465V 5 µA CLK1 V IN = VDD = 3.465V 150 µA IIL Input Low Current nCLK1 V IN = 0V, VDD = 3.465V -150 µA CLK1 V IN = 0V, VDD = 3.465V -5 µA VPP Peak-to-Peak Input Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD - 0.85 V NOTE 1: For single ended applications, the maximum input voltage for CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defi ned as VIH. TABLE 5A. AC CHARACTERISTICS, VDD = VDDOX = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 2.8 3.2 3.7 ns CLK1, nCLK1; NOTE 1B 2.9 3.4 3.9 ns tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 150 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps tR / tF Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps odc Output Duty Cycle f < 175MHz 45 55 % f ≥ 175MHz 40 60 % tEN Output Enable Time; NOTE 6 10 ns tDIS Output Disable Time; NOTE 6 10 ns All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defi ned as skew within a bank with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDOX/2. NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at V DDOX/2. NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

6 REVISION C 06/26/15

TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDOX = 2.5V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 2.9 3.3 3.8 ns CLK1, nCLK1; NOTE 1B 3 3.5 4 ns tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 160 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps tR / tF Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps odc Output Duty Cycle f < 175MHz 45 55 % f ≥≥≥ 175MHz 40 60 % tEN Output Enable Time; NOTE 6 10 ns tDIS Output Disable Time; NOTE 6 10 ns All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defi ned as skew within a bank with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDOX/2. NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at V DDOX/2. NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

7 LOW SKEW, 1-TO-16

LVCMOS/LVTTL CLOCK GENERATOR TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDOX = 1.8V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units fMAX Output Frequency 250 MHz tpLH Propagation Delay, Low to High CLK0; NOTE 1A 3.1 3.8 4.5 ns CLK1, nCLK1; NOTE 1B 3.1 3.8 4.5 ns tsk(b) Bank Skew; NOTE 2, 7 Measured on the Rising Edge 30 ps tsk(o) Output Skew; NOTE 3, 7 Measured on the Rising Edge 170 ps tsk(pp) Part-to-Part Skew; NOTE 5, 7 750 ps tR / tF Output Rise/Fall Time; NOTE 6 20% to 80% 200 700 ps odc Output Duty Cycle f < 175MHz 45 55 % f ≥ 175MHz 40 60 % tEN Output Enable Time; NOTE 6 10 ns tDIS Output Disable Time; NOTE 6 10 ns All parameters measured at 250MHz unless noted otherwise. NOTE 1A: Measured from the VDD/2 of the input to VDDOX/2 of the output. NOTE 1B: Measured from the differential input crossing point to VDDOX/2 of the output. NOTE 2: Defi ned as skew within a bank with equal load conditions. NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDOX/2. NOTE 4: Defi ned as skew across banks of outputs switching in the same direction operating at different frequencies with the same supply voltages and equal load conditions. Measured at V DDOX/2. NOTE 5: Defi ned as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at V DDOX/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defi ned in accordance with JEDEC Standard 65.

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

8 REVISION C 06/26/15

PARAMETER MEASUREMENT INFORMATION 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART-TO-PART SKEW OUTPUT SKEW

9 LOW SKEW, 1-TO-16

LVCMOS/LVTTL CLOCK GENERATOR PROPAGATION DELAY BANK SKEW (where X denotes outputs in the same bank) OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

10 REVISION C 06/26/15

APPLICATION INFORMATION

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 1kΩ resistor can be tied from the CLK input to ground. protection. A 1kΩ resistor can be used. that there is no trace attached.

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LVCMOS/LVTTL CLOCK GENERATOR FIGURE 2C. CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2B. CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. CLK/ NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V Zo = 50 Ohm LVPECL Zo = 50 Ohm HiPerClockS CLK nCLK 3.3V Input Zo = 50 Ohm Input HiPerClockS CLK nCLK 3.3V 125 Zo = 50 Ohm 3.3V 125 LVPECL 3.3V DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver FIGURE 2A. CLK/ NCLK INPUT DRIVEN BY LVHSTL DRIVER component to confi rm the driver termination requirements. For example in Figure 2A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V Input LVHSTL Driver ICS HiPerClockS LVHSTL 3.3V Zo = 50 Ohm Zo = 50 Ohm HiPerClockS CLK nCLK FIGURE 2E. CLK/ NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE Zo = 50 Ohm 125 HiPerClockS CLK nCLK 3.3V 100 - 200 3.3V 3.3V 100 - 200 Input R5,R6 locate near the driver pin. Zo = 50 Ohm 125 LVPECL C1 Zo = 50 Ohm 100 3.3V LVDS_Driv er Zo = 50 Ohm Receiver CLK nCLK 3.3V

12 REVISION C 06/26/15

Figure 3 shows an application schematic example of the 87016. This schematic provides examples of input and output handling. FIGURE 3. APPLICATION SCHEMATIC EXAMPLE in the LVCMOS Termination Application Note.

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TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

14 REVISION C 06/26/15

TABLE 7. PACKAGE DIMENSIONS

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TABLE 8. ORDERING INFORMATION NOTE: Parts that are ordered with an “LF” suffi x to the part number are the Pb-Free confi guration and are RoHS compliant.

8 Quadrant 1 (EIA-481-C)

TABLE 9. PIN 1 ORIENTATION IN TAPE AND REEL PACKAGING

LOW SKEW, 1-TO-16 LVCMOS/LVTTL CLOCK GENERATOR

16 REVISION C 06/26/15

Rev Table Page Description of Change Date A T5A, T5B, T5C 6, 7, AC Characteristics Table - corrected the fi rst line in the Notes section, from “All parameters measured at 150MHz...” to 250MHz. 7/31/02 A Revised part description title from “Differential-to-LVCMOS Clock Generator” to “LVCMOS Clock Generator”. 8/9/02 A T5A & T5B 6 & 7 AC Characteristics Table - switched prop delay values for CLK0 and CLK1, nCLK1. Added Differential Clock Input Interface section. Updated format. 5/05/03 A 1 Modifi ed Block Diagram, corrected latch block. 6/4/03 A 12 Added Schematic Example 12/10/04 A Features Section - added Lead-Free bullet. Application Section - added Recommendations for Unused Input and Output Pins. Ordering Information Table - add Lead-Free part number, marking and note. 2/28/06 AT 8 1 5 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefi x from Part/Order Number column. Added Contact Page. 7/29/10 B T4B 4 LVCMOS DC Characteristics Table - corrected typo for 1.8V V OH min. spec from VDD - 0.45 to VDDOx - 0.45. 4/4/13 C Updated datasheet format. Features section - removed reference to leaded device. Ordering Information - removed leaded devices - PDN CQ-13-02. 1/12/15 C T9 15 Added Pin 1 Orientation in Tape and Reel Packaging Table. 6/26/15

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