87004AGLF

ICS87004 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: epieczon
• PDF pages: 16

Technical content

Features

• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
• CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration with configurable frequencies
• Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 50ps (maximum)
• Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0
• Full 3.3V or 2.5V output operating supply
• 5V tolerant inputs
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS GND VDDO SEL0 SEL1 SEL2 SEL3 CLK_SEL VDD CLK0 nCLK0 GND VDDO GND VDDO MR FB_IN PLL_SEL CLK1 nCLK1 VDDA ICS87004 24-Lead TSSOP 7.8mm x 4.4mm x 0.925mm package body G Package Top View Block Diagram PLL_SEL FB_IN SEL0 SEL1 SEL2 SEL3 MR CLK0 nCLK0 PLL 1:2, 1:4, 1:8 ÷2, ÷4, ÷8, ÷16 ÷32, ÷64, ÷128 Pullup/Pulldown Pulldown CLK_SEL Pulldown Pulldown Pulldown CLK1 nCLK1 Pullup/Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pin Assignment

ICS87004AG REVISION C DECEMBER 1, 2009 2 ©2009 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 12, 21 GND Power Power supply ground. Q2, Q1 Output Single-ended clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels. 3, 19, 23 V DDO Power Output supply pins. SEL2, SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels. 9V DD Power Core supply pin. 10 CLK0 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 default when left floating. 13 V DDA Power Analog supply pin. Pulldown Inverting differential clock input. VDD/2 default when left floating. 15 CLK1 Input Pulldown Non-inverting differential clock input.

16 PLL_SEL Input Pullup

selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels. Connect to one of the outputs. LVCMOS/LVTTL interface levels.

18 MR Input Pulldown

outputs are enabled. LVCMOS / LVTTL interface levels.

ICS87004AG REVISION C DECEMBER 1, 2009 3 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. PLL Enable Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q[0:3] 0000 1 2 5 - 2 5 0 ÷ 1 0001 6 2 . 5 - 1 2 5 ÷ 1 0010 3 1 . 2 5 - 6 2 . 5 ÷ 1 0011 1 5 . 625 - 31.25 ÷1 0100 1 2 5 - 2 5 0 ÷ 2 0101 6 2 . 5 - 1 2 5 ÷ 2 0110 3 1 . 2 5 - 6 2 . 5 ÷ 2 0111 1 2 5 - 2 5 0 ÷ 4 1000 6 2 . 5 - 1 2 5 ÷ 4 1001 1 2 5 - 2 5 0 ÷ 8 1010 6 2 . 5 - 1 2 5 x 2 1011 3 1 . 2 5 - 6 2 . 5 x 2 1100 1 5 . 625 - 31.25 x2 1101 3 1 . 2 5 - 6 2 . 5 x 4 1110 1 5 . 625 - 31.25 x4 1111 1 5 . 625 - 31.25 x8

ICS87004AG REVISION C DECEMBER 1, 2009 4 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q[0:3] 0000 ÷ 8 0001 ÷ 8 0010 ÷ 8 0011 ÷ 1 6 0100 ÷ 1 6 0101 ÷ 1 6 0110 ÷ 3 2 0111 ÷ 3 2 1000 ÷ 6 4 1001 ÷ 1 2 8 1010 ÷ 4 1011 ÷ 4 1100 ÷ 8 1101 ÷ 2 1110 ÷ 4 1111 ÷ 2

ICS87004AG REVISION C DECEMBER 1, 2009 5 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 6m A Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 96 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 6m A

ICS87004AG REVISION C DECEMBER 1, 2009 6 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams. Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current SEL[0:3], MR, FB_IN, CLK_SEL VDD = VIN = 3.465V or 2.625V 150 µA PLL_SEL V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current SEL[0:3], MR, FB_IN, CLK_SEL V DD = 3.465V or 2.625V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 V DD = 3.465V or 2.625V 0.5 V Symbol Parameter Test Conditio ns Minimum Typical Maximum Units IIH Input High Current CLK0/nCLK0, CLK1/nCLK1 V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK0, CLK1 V DD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK0, nCLK1 V DD = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V

ICS87004AG REVISION C DECEMBER 1, 2009 7 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at V DDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tPD Propagation Delay; NOTE 1 CLK0, nCLK0 CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 56 . 2 n s t(Ø) Static Phase Offset; NOTE 2, 4 CLK0, nCLK0 PLL_SEL = 3.3V, f REF ≤ 167MHz, Qx ÷ 1 -75 50 175 ps CLK1, nCLK1 -190 -65 175 ps tsk(o) Output Skew; NOTE 3, 4 CLK0, nCLK0 CLK1, nCLK1 PLL_SEL = 0V 40 50 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 30 45 ps tL PLL Lock Time 1m s tR / tF Output Rise/Fall Time 20% to 80% 400 800 ps odc Output Duty Cycle 40 50 60 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tPD Propagation Delay; NOTE 1 CLK0, nCLK0 CLK1, nCLK1 PLL_SEL = 0V, f ≤ 250MHz, Qx ÷ 2 5.3 6.9 ns t(Ø) Static Phase Offset; NOTE 2, 4 CLK0, nCLK0 PLL_SEL = 2.5V, f REF ≤ 167MHz, Qx ÷ 1 -175 -25 125 ps CLK1, nCLK1 -290 -115 125 ps tsk(o) Output Skew; NOTE 3, 4 CLK0, nCLK0 CLK1, nCLK1 PLL_SEL = 0V 40 45 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 35 45 ps tL PLL Lock Time 1m s tR / tF Output Rise/Fall Time 20% to 80% 400 700 ps odc Output Duty Cycle 44 50 56 %

ICS87004AG REVISION C DECEMBER 1, 2009 8 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V Output Load AC Test Circuit Differential Input Level Cycle-to-Cycle Jitter 2.5V Output Load AC Test Circuit Output Skew Static Phase Offset SCOPE QxLVCMOS GND VDDA, VDDO VDD, 1.65V±5% -1.65V±5% nCLK[0:1] CLK[0:1] VDD GND V CMR Cross Points V PP Q[0:3] ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|

1000 Cycles

1.25V±5% -1.25V±5% VDD, VDDA, VDDO Qx Qy tsk(o) VDDO VDDO nCLK[0:1] CLK[0:1] FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL VDDO t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges.

ICS87004AG REVISION C DECEMBER 1, 2009 9 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued Output Rise/Fall Time Propagation Delay Output Duty Cycle/Pulse Width/Period 20% 80% 80% 20% tR tF Q[0:3] tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q[0:3] t PD VDDO nCLK[0:1] CLK[0:1] Q[0:3]

ICS87004AG REVISION C DECEMBER 1, 2009 12 ©2009 Integrated Device Technology, Inc. Table 6. θJA vs. Air Flow Table for a 24 Lead TSSOP

ICS87004AG REVISION C DECEMBER 1, 2009 13 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR

Ordering Information

Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

ICS87004AG REVISION C DECEMBER 1, 2009 14 ©2009 Integrated Device Technology, Inc. ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR Revision History Sheet Rev Table Page Description of Change Date B T5A T5B 3.3V AC Characteristics Table - adjusted t PD parameter from 6ns max. to 6.2ns max. Added Recommendations for Unused Input and Output Pins section. 10/7/05 C T4D T5A, T5B Differential DC Characteristics Table - updated NOTES 1, 2. AC Characteristics Tables - Static Phase Offset, split CLKx into 2 rows. Specs changed for CLK1/nCLK1. Added Thermal note. Updated Differential Clock Input Interface section. Ordering Information Table - deleted “ICS” prefix from Part/Order Number column. Converted datasheet format. 10/6/09 C 1 Features section - corrected output sk ew from 465ps ot 50ps (maximum) 12/1/09

ICS87004 Data Sheet 1:4, DIFFERENTIAL-TO-L VCMOS/LVTTL ZERO DELAY CLOCK GENERATOR DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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