87002-02 RENESAS | Alldatasheet
Document overview
- Manufacturer or author: rdvorak
- PDF pages: 17
Technical content
Features
- Two LVCMOS/LVTTL outputs, 7 typical output impedance
- CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
- Internal bias on nCLK to support LVCMOS/LVTTL levels on CLK input
- Output frequency range: 15.625MHz to 250MHz
- Input frequency range: 15.625MHz to 250MHz
- VCO range: 250MHz to 500MHz
- External feedback for “zero delay” clock regeneration with configurable frequencies
- Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
- Fully integrated PLL
- Cycle-to-cycle jitter: 45ps (maximum)
- Output skew: 35ps (maximum)
- Static phase offset: -10ps ± 150ps (3.3V ± 5%)
- Full 3.3V or 2.5V operating supply
- 5V tolerant inputs
- 0°C to 70°C ambient operating temperature
- Available in lead-free (RoHS 6) package
- Industrial temperature information available upon request CLK VDD SEL3 SEL2 SEL1 SEL0 VDDO GND nCLK VDDO GND VDDO nc MR FB_IN PLL_SEL VDDA GND 87002-02 20-Lead TSSOP 6.50mm x 4.40mm x 0.925mm package body G Package Top View Block Diagram PLL_SEL FB_IN SEL0 SEL1 SEL2 SEL3 MR CLK nCLK PLL 1:2, 1:4, 1:8 ÷2, ÷4, ÷8, ÷16 ÷32, ÷64, ÷128 Pullup/Pulldown Pulldown Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pin Assignment
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Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 11, 18 GND Power Power supply ground. 2, 19 Q0, Q1 Output Single-ended clock outputs. 7 typical output impedance. LVCMOS/LVTTL interface levels. 3, 17, 20 V DDO Power Output supply pins. SEL2, SEL3 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 8V DD Power Core supply pin. 9 CLK Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential clock input. VDD/2 default when left floating. 12 V DDA Power Analog supply pin.
13 PLL_SEL Input Pullup
PLL (PLL enabled). LVCMOS/LVTTL interface levels. Connect to one of the outputs. LVCMOS/LVTTL interface levels.
15 MR Input Pulldown
enabled. LVCMOS / LVTTL interface levels.
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Table 3A. PLL Enable Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0, Q1 0000 1 2 5 - 2 5 0 ÷ 1 0001 6 2 . 5 - 1 2 5 ÷ 1 0010 3 1 . 2 5 - 6 2 . 5 ÷ 1 0011 1 5 . 6 2 5 - 3 1 . 2 5 ÷ 1 0100 1 2 5 - 2 5 0 ÷ 2 0101 6 2 . 5 - 1 2 5 ÷ 2 0110 3 1 . 2 5 - 6 2 . 5 ÷ 2 0111 1 2 5 - 2 5 0 ÷ 4 1000 6 2 . 5 - 1 2 5 ÷ 4 1001 1 2 5 - 2 5 0 ÷ 8 1010 6 2 . 5 - 1 2 5 x 2 1011 3 1 . 2 5 - 6 2 . 5 x 2 1100 1 5 . 6 2 5 - 3 1 . 2 5 x 2 1101 3 1 . 2 5 - 6 2 . 5 x 4 1110 1 5 . 6 2 5 - 3 1 . 2 5 x 4 1111 1 5 . 6 2 5 - 3 1 . 2 5 x 8
Rev C 7/13/15 4 1:2, DIFFERENTIAL-TO- LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q0, Q1 0000 ÷ 8 0001 ÷ 8 0010 ÷ 8 0011 ÷ 1 6 0100 ÷ 1 6 0101 ÷ 1 6 0110 ÷ 3 2 0111 ÷ 3 2 1000 ÷ 6 4 1001 ÷ 1 2 8 1010 ÷ 4 1011 ÷ 4 1100 ÷ 8 1101 ÷ 2 1110 ÷ 4 1111 ÷ 2
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NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 100 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 6m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VDD Core Supply Voltage 2.375 2.5 2.625 V VDDA Analog Supply Voltage 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 96 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 6m A
Rev C 7/13/15 6 1:2, DIFFERENTIAL-TO- LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: Outputs terminated with 50 to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams. Table 4D. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VDD = 3.3V 2 V DD + 0.3 V VDD = 2.5V 1.7 V DD + 0.3 V VIL Input Low Voltage VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V IIH Input High Current FB_IN, SEL[0:3], MR VDD = VIN = 3.465V or 2.625V 150 µA PLL_SEL V DD = VIN = 3.465V or 2.625V 5 µA IIL Input Low Current FB_IN, SEL[0:3], MR VDD = 3.465V or 2.625V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V or 2.625V, VIN = 0V -150 µA VOH Output High Voltage; NOTE 1 VDDO = 3.465V 2.6 V VDDO = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 V DDO = 3.465V or 2.625V 0.5 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V or 2.625V 150 µA nCLK V DD = VIN = 3.465V or 2.625V 150 µA IIL Input Low Current CLK V DD = 3.465V or 2.625V, VIN = 0V -5 µA nCLK V DD = 3.465V or 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V
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Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at VDDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Table 5B. AC Characteristics, VDD = VDDA = VDDO = 2.5V ± 5%, TA = 0°C to 70°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the output at V DDO/2. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V DDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tPD Propagation Delay; NOTE 1 PLL_SEL = 0V, f 250MHz, Qx ÷ 2 4.8 5.8 ns t(Ø) Static Phase Offset; NOTE 2, 4 PLL_SEL = 3.3V, fREF 167MHz, Qx ÷ 1 -160 -10 140 ps tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 40 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 45 ps tL PLL Lock Time 1m s tR / tF Output Rise/Fall Time 20% to 80% 400 800 ps odc Output Duty Cycle 40 60 % Symbol Parameter Test Conditio ns Minimum Typical Maximum Units fMAX Output Frequency 15.625 250 MHz tPD Propagation Delay; NOTE 1 PLL_SEL = 0V, f 250MHz, Qx ÷ 2 4.9 6.7 ns t(Ø) Static Phase Offset; NOTE 2, 4 PLL_SEL = 2.5V, fREF 167MHz, Qx ÷ 1 -240 -65 110 ps tsk(o) Output Skew; NOTE 3, 4 PLL_SEL = 0V 35 ps tjit(cc) Cycle-to-Cycle Jitter; NOTE 4 f OUT > 40MHz 45 ps tL PLL Lock Time 1m s tR / tF Output Rise/Fall Time 20% to 80% 400 700 ps odc Output Duty Cycle 44 56 %
Rev C 7/13/15 8 1:2, DIFFERENTIAL-TO- LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET Parameter Measurement Information 3.3V Output Load AC Test Circuit Differential Input Level Cycle-to-Cycle Jitter 2.5V Output Load AC Test Circuit Output Skew Static Phase Offset SCOPE Qx GND VDDA, VDDO VDD, 1.65V±5% -1.65V±5% nCLK CLK VDD GND V CMR Cross Points V PP Q0, Q1 ➤➤ ➤➤ VDDO VDDO VDDO tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
1.25V±5% -1.25V±5% VDD, VDDA, VDDO Qx Qy tsk(o) VDDO VDDO nCLK CLK FB_IN ➤ ➤t(Ø) VOH VOL VOH VOL VDDO t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges.
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Parameter Measurement Information, continued Output Rise/Fall Time Propagation Delay Output Duty Cycle/Pulse Width/Period 20% 80% 80% 20% tR tF Q0, Q1 tPERIOD tPW tPERIOD odc = VDDO x 100% tPW Q0, Q1 t PD VDDO nCLK CLK Q0, Q1
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Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 50Ω 50Ω 1.8V Zo = 50Ω Zo = 50Ω CLK nCLK 3.3V LVHSTL IDT LVHSTL Driver Differential Input HCSL *R3 *R4 CLK nCLK 3.3V 3.3V Differential Input CLK nCLK Differential InputSSTL 2.5V Zo = 60Ω Zo = 60Ω 2.5V 3.3V 120Ω 120Ω 120Ω 120Ω
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Table 6. JA vs. Air Flow Table for a 20 Lead TSSOP NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Rev C 7/13/15 14 1:2, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR 87002-02 DATA SHEET
Ordering Information
Table 8. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
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Rev Table Page Description of Change Date B Pin Characteristics Table - added C PD specs. Added Recommendations for Unused Input and Output Pins section. Updated Differential Clock Input Interface section. Added Schematic Layout Ordering Information Table - added Lead-Free marking. 4/29/08 C T5A, T5B T5B Added thermal note. 2.5V AC Characteristics Table - due to datasheet conversion on April 29, 2008, corrected typo for static phase offset spec from -650 to -65. Updated Wiring the Differential Levels to Accept Single-ended Levels section. Ordering Information Table - deleted “ICS” prefix from the Part/Order Number column. Updated header/footer of datasheet. 8/9/10 Updated data sheet format. 7/13/15
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