85C72 MICROCHIP | Alldatasheet
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Technical content
Ó 1995 Microchip Technology Inc. DS11182C-page 1
FEATURES
- Low power CMOS technology
- Two wire serial interface bus, I C Ô compatible
- 5 volt only operation
- Self-timed write cycle (including auto-erase)
- Page-write buffer
- 1ms write cycle time for single byte
- 1,000,000 ERASE/WRITE cycles guaranteed
- Data retention >200 years
- 8-pin DIP or SOIC package
- Available for extended temperature ranges: - Commercial: 0˚C to +70˚C - Industrial: -40˚C to +85˚C - Automotive: -40˚C to +125˚C
DESCRIPTION
The Microchip Technology Inc. 85C72/82/92 is a 1K/ 2K/4K bit Electrically Erasable PROM. The device is organized as shown with a two wire serial interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. The 85C72/82/92 also has a page-write capability for up to 8 bytes of data (see chart). Up to eight 85C72/82/92s may be connected to the two wire bus. The 85C72/82/ 92 is available in standard 8-pin DIP and surface mount SOIC packages. 85C72 85C82 85C92 Organization 128 x 8 256 x 8 2 x 256 x 8 Page Write Buffer
2 Bytes 2 Bytes 8 Bytes
V SS V NC SCL SDA CC V NC SCL SDA CCA0 V SS NC SS CCA0 NC NC V NC SCL SDA NC V NC NC DIP 8-lead SOIC 14-lead SOIC 85C72 85C82 85C92 85C72 85C82 85C92 85C92 R/W AMPVPP A D D R E S S P O I N T E R MEMORY ARRAYSLAVE ADR. DATA REG. DATA BUFFER (FIF0) CONTROL LOGIC SDA V CC VSS SCL A0 A2 A0 to INCREMENT 85C72/82/92 1K/2K/4K 5.0V CMOS Serial EEPROM I C is a trademark of Philips Corporation
Ó 1995 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
V CC All inputs and outputs w.r.t. V SS CC +1.0V Soldering temperature of leads (10 seconds) ...+300˚C *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rat- ing only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: PIN FUNCTION TABLE Name Function A0, A1, A2 Chip Address Inputs V SS Ground SDA Serial Address/Data Input/Output SCL Serial Clock NC No Connect V CC +5V Power Supply TABLE 1-2: DC CHARACTERISTICS FIGURE 1-1: BUS TIMING START/STOP V CC = +5V (10%) Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C Automotive (E): Tamb = -40˚C to 125˚C Parameter Symbol Min Max Units Conditions V CC detector threshold V TH 2.8 4.5 V SCL and SDA pins: High level input voltage V IH V CC x 0.7 V CC + 1 V Low level input voltage V IL -0.3 V CC X 0.3 V Low level output voltage V OL
0.4 V I
= 3.2 mA (SDA 0nly) A0, A1 & A2 pins: HIgh level input voltage V IH V CC - 0.5 V CC + 0.5 V Low level input voltage V IL -0.3 0.5 V Input leakage current I LI —1 0 m AV IN = 0V TO Vcc Output leakage current I LO —1 0 m AV OUT = 0V TO Vcc Pin capacitance (all inputs/outputs) C IN C OUT — 7.0 pF V IN OUT = 0V (Note 1) Tamb = +25˚C, f = 1 MHz Operating current read cycle I CCO I CCR 3.5 4.25 750 mA mA m A F CLK = 100 kHz, program cycle time = 1 ms, V CC = 5V, Tamb = 0˚C to +70˚C F CLK = 100 kHz, program cycle time = 1 ms, V CC = 5V, Tamb = (I) and (E) V CC = 5V, Tamb = (C), (I) and (E) Standby current I CCS — 100 m A SDA=SCL=V CC =5V (no PROGRAM active) Note 1: This parameter is periodically sampled and not 100% tested. SCL SDA START STOP TSU:STA THD:STA TSU:STO VHYS
Ó 1995 Microchip Technology Inc. DS11182C-page 3 85C72/82/92 TABLE 1-3: AC CHARACTERISTICS Parameter Symbol Min Typ Max Units Remarks Clock frequency F CLK — — 100 kHz Clock high time T HIGH 4000 — — ns Clock low time T LOW 4700 — — ns SDA and SCL rise time T R — — 1000 ns SDA and SCL fall time T F — — 300 ns START condition hold time T HD:STA 4000 — — ns After this period the first clock pulse is generated START condition setup time T SU:STA 4700 — — ns Only relevant for repeated START condition Data input hold time T HD DAT 0— —n s Data input setup time T SU DAT 250 — — ns Data output delay time T PD 300 — 3500 ns Note 1 STOP condition setup time T SU STO 4700 — — ns Bus free time T BUF 4700 — — ns Time the bus must be free before a new transmission can start Input filter time constant (SDA and SCL pins) T I — — 100 ns Program cycle time T WC —. 4 .4N N ms ms Byte Mode Page Mode, N = # of bytes to be written Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (min- imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. FIGURE 1-2: BUS TIMING DATA SU:STAt HD:STAt Ft LOWt HIGHt Rt SU:STOt BUFtt AAt SDA OUT SDA IN SCL HD:DATt SU:DATt AA
Ó 1995 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 85C72/82/92 supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and gener- ates the START and STOP conditions, while the 85C72/82/92 works as slave. Both, master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. Up to eight 85C72/82/92s can be connected to the bus, selected by the A0, A1 and A2 chip address inputs. Other devices can be connected to the bus, but require different device codes than the 85C72/82/92 (refer to section Slave Address).
3.0 BUS CHARACTERISTICS
has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (see Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data T ransfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condi- tion.
3.3 Stop Data T ransfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.
3.4 Data V alid (D)
The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case the slave must leave the data line HIGH to enable the master to generate the STOP condition Note: The 85C72/82/92 does not generate any acknowledge bits if an internal program- ming cycle is in progress. FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS SCL SDA (A) (B) (D) (D) (C) (A) START CONDITION ADDRESS OR ACKNOWLEDGE VALID DATA ALLOWED TO CHANGE STOP CONDITION
Ó 1995 Microchip Technology Inc. DS11182C-page 5 85C72/82/92
4.0 SLAVE ADDRESS
The chip address inputs A0, A1 and A2 of each 85C72/ 82/92 must be externally connected to either V CC or ground (V SS ), assigning to each 85C72/82/92 a unique 3-bit address. Up to eight 85C72/82/92s may be con- nected to the bus. Chip selection is then accomplished through software by setting the bits A0, A1 and A2 of the transmitted slave address to the corresponding hardwired logic levels of the selected 85C72/82/92. After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010) for the 85C72/82/92, followed by the chip address bits A0, A1 and A2. In the 85C92 the seventh bit of that byte (BA) is used to select the upper block (addresses 100 - 1FF) or the lower block (000 - FFF) of the array. The eighth bit of slave address determines if the master device wants to read or write to the 85C72/82/92 (see Figure 4-1). The 85C72/82/92 monitors the bus for its correspond- ing slave address all the time. It generates an acknowl- edge bit if the slave address was true and it is not in a programming mode. FIGURE 4-1: SLAVE ADDRESS ALLOCATION START READ/WRITE SLAVE ADDRESS R/W 1 0 1 0 A 2A 1A 0 A
5.0 BYTE PROGRAM MODE
In this mode, the master sends addresses and one data byte to the 85C72/82/92. Following the START condition, the device code (4-bit), the slave address (3-bit), and the R/W bit, which is logic LOW, are placed onto the bus by the master. This indi- cates to the addressed 85C72/82/92 that a byte with a word address will follow after it has generated an acknowledge bit. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 85C72/82/92. After receiving the acknowledge of the 85C72/82/92, the master device transmits the data word to be written into the addressed memory location. The 85C72/82/92 acknowledges again and the master generates a STOP condition. This initiates the internal program- ming cycle of the 85C72/82/92 (see Figure 6-1).
6.0 PAGE PROGRAM MODE
To program the 85C72/82/92, the master sends addresses and data to the 85C72/82/92 which is the slave (see Figure 6-1). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address, and the R/W bit which is defined as a logic LOW for a write. This indicates to the addressed slave that a word address will follow so the slave out- puts the acknowledge pulse to the master during the ninth clock pulse. When the word address is received by the 85C72/82/92, it places it in the lower 8 bits of the address pointer defining which memory location is to be written. The 85C72/82/92 will generate an acknowl- edge after every 8 bits received and store them con- secutively in a 2-byte RAM until a stop condition is detected which initiates the internal programming cycle. If more than 2 bytes are transmitted by the mas- ter, the 85C72/82/92 will terminate the write cycle. This does not affect erase/write cycles of the EEPROM array. If the master generates a STOP condition after trans- mitting the first data word (Point ‘P’ on Figure 6-1), byte programming mode is entered. The internal, completely self-timed PROGRAM cycle starts after the STOP condition has been generated by the master and all received (up to two) data bytes will be written in a serial manner. The PROGRAM cycle takes N milliseconds, whereby N is the number of received data bytes (N max = 2). FIGURE 6-1: PROGRAM MODE (ERASE/WRITE) START STOPADATA BYTE NDATA BYTE 1 AAWORD ADDRESSA0 R/W P ACKNOWLEDGES FROM SLAVE SLAVE ADDRESS
Ó 1995 Microchip Technology Inc.
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow dia- gram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Next Operation No Yes
8.0 READ MODE
This mode illustrates master device reading data from the 85C72/82/92. As can be seen from Figure 8-1, the master first sets up the slave and word addresses by doing a write. During this period the 85C72/82/92 generates the nec- essary acknowledge bits as defined in the appropriate section. The master now generates another START condition and transmits the slave address again, except this time the read/write bit is set into the read mode. After the slave generates the acknowledge bit, it then outputs the data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This autoincrement sequence is only aborted when the master sends a STOP condition instead of an acknowledge. Note: Although this is a read mode, the address pointer must be written to. Note 1: If the master knows where the address pointer is, it can begin the read sequence at point ‘R’ indicated on Figure 8-1 and save time transmitting the slave and word addresses. Note 2: In all modes, the address pointer will auto- matically increment from the end of the memory block (256 byte) back to the first location in that block. FIGURE 8-1: READ MODE R START A WORD ADDRESSA0 R/W ACKNOWLEDGES FROM SLAVE RECEIVER STARTSLAVE ADDRESS 1 STOPLAST DATA BYTE SLAVE ADDRESS A R/W AUTO INCREMENT WORD ADDRESS ADATA BYTE 1 ACKNOWLEDGES FROM MASTER RECEIVER
Ó 1995 Microchip Technology Inc. DS11182C-page 7 85C72/82/92
9.0 PIN DESCRIPTION
9.1 A0, A1 and A2 Chip Address Inputs
The levels on these inputs are compared with the cor- responding bits in the slave address. The chip is selected if the compare is true. For 85C92, A0 is no function. Up to eight 85C72/82s or four 85C92s can be con- nected to the bus. These inputs must be connected to either V SS or VCC .
9.2 SDA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to V CC (typical 10KW). For normal data trans- fer SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions.
9.3 SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
9.4 NC No Connect
This pin can be left open or used as a tie point. Note 1:A “page” is defined as the maximum num- ber of bytes that can be programmed in a single write cycle. The 85C72/82 page is 2 bytes long and the 85C92 page is 8 bytes long. Note 2:A “block” is defined as a continuous area of memory with distinct boundaries. The address pointer can not cross the bound- ary from one block to another. It will, how- ever, wrap around from the end of a block to the first location in the same block. The 85C72/82 has only one block (256 bytes), while the 85C92 has two blocks of 256 bytes each.
DS11182C-page 8 Ó 1995 Microchip Technology Inc. 85C72/82/92 Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. Package: P = Plastic DIP (300 mil Body), 8-lead SM = Plastic SOIC (207 mil Body), 8-lead SL = Plastic SOIC 14-lead (85C92 only) Temperature Blank = 0°C to +70°C Range: I = -40°C to +85°C E = -40°C to +125°C Device: 85C72 1K CMOS Serial EEPROM 85C72T 1K CMOS Serial EEPROM (Tape and Reel) 85C82 2K CMOS Serial EEPROM 85C82 2K CMOS Serial EEPROM (Tape and Reel) 85C92 4K CMOS Serial EEPROM 85C92T 4K CMOS Serial EEPROM (Tape and Reel) 85C82 - /P AMERICAS (continued) San Jose Microchip Technology Inc.
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Hauppauge, NY 11788 Tel: 516 273-5305 Fax: 516 273-5335 "Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. Printed in the USA, 9/95 Ó 1995, Microchip Technology Incorporated