ICS859S0212I RENESAS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Features
- High speed 2:1 differential multiplexer with a 1:2 fanout buffer
- Two differential LVPECL or LVDS output pairs
- Two selectable differential PCLKx, nPCLKx input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML
- Maximum output frequency: 3GHz
- Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
- Part-to-part skew: 100ps (maximum)
- Propagation delay: 565ps (typical) at 3.3V
- Additive phase jitter, RMS: 0.21ps (typical) at 3.3V
- Full 3.3V or 2.5V supply modes
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package ICS859S0212I 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram 9SEL_OUT OE nc nPCLK1 PCLK1 nPCLK0 PCLK0 CLK_SEL VCC VEE nQ0 nQ1 VEE VCC_TAP PCLK0 CLK_SEL OE nPCLK0 PCLK1 nPCLK1 nQ0 nQ1 Pullup/Pulldown Pulldown Pulldown Pullup SEL_OUT Pullup Pullup/Pulldown Pulldown
ICS859S0212BGI REVISION A JUNE 4, 2012 2 ©2012 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1 CLK_SEL Input Pulldown Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels. 2 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input. Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 4 PCLK1 Input Pulldown Non-inverting differential clock input. Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 7 OE Input Pullup Output enable pin. See Table 4B. LVCMOS/LVTTL interface levels. levels. LVCMOS/LVTTL interface levels. See Table 3B. 9V CC_TAP Power Positive supply pin. See Table 3A. 10, 15 V EE Power Negative supply pins. 11, 12 nQ1, Q1 Output Differential output pair. LVPECL or LVDS interface levels. 13, 14 nQ0, Q0 Output Differential output pair. LVPECL or LVDS interface levels. 16 V CC Power Positive supply pin.
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 3 ©2012 Integrated Device Technology, Inc. Function Tables Table 3A. VCC_TAP Function Table Table 4A. Clock Input Function Table Table 3B. SEL_OUT Function Table Table 4B. Output Enable Function Table Outputs Output Level Supply V CC_TAPQ[0:1], nQ[0:1] LVPECL 2.5V VCC LVPECL 3.3V VCC LVDS 2.5V VCC LVDS 3.3V Float Inputs Outputs CLK_SEL Q[0:1], nQ[0:1] 0 (default) PCLK0, nPCLK0
1 PCLK, nPCLK1
SEL_OUT Q[0:1], nQ[0:1] 1 (default) LVPECL 0L VDS Inputs Outputs OE Q[0:1], nQ[0:1]
0 Low, High
1 (default) Normal Operation
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 4 ©2012 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5B. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Table 5C. LVDS Power Supply DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Table 5D. LVDS Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, IO (LVDS) Continuos Current Surge Current 50mA 100mA 10mA 15mA Package Thermal Impedance, JA 92C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 3.135 3.3 3.465 V VCC_TAP Positive Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 55 mA ICC_TAP Power Supply Current 5m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 2.5 2.625 V VCC_TAP Positive Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 50 mA ICC_TAP Power Supply Current 5m A Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 80 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 2.5 2.625 V VCC_TAP Positive Supply Voltage 2.375 2.5 2.625 V ICC Power Supply Current 76 mA ICC_TAP Power Supply Current 5m A
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 5 ©2012 Integrated Device Technology, Inc. Table 5E. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Table 5F. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: Outputs terminated with 50 to VCC – 2V. Table 5G. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE 1: Common mode input voltage is defined as VIH. NOTE 1: Outputs terminated with 50 to VCC – 2V. Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage VCC = 3.465V 2.2 VCC + 0.3 V VCC = 2.625V 1.7 VCC + 0.3 V VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V VCC = 2.625V -0.3 0.7 V IIH Input High Current CLK_SEL V CC = VIN = 3.465V or 2.625V 150 µA OE, SEL_OUT VCC = VIN = 3.465V or 2.625V 10 µA IIL Input Low Current CLK_SEL V CC = 3.465V or 2.625V, VIN = 0V -10 µA OE, SEL_OUT V CC = 3.465V or 2.625V, VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typic al Maximum Units IIH Input High Current PCLK0, PCLK1, nPCLK0, nPCLK1 V CC = VIN = 3.465V 150 µA IIL Input Low Current PCLK0, PCLK1 V CC = 3.465V, VIN = 0V -10 µA nPCLK0, nPCLK1 V CC = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 1.2 V CC V VOH Output High Voltage; NOTE 2 VCC – 1.4 VCC – 0.9 V VOL Output Low Voltage; NOTE 2 VCC – 2.0 VCC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK0, PCLK1, nPCLK0, nPCLK1 VCC = VIN = 2.625V 150 µA IIL Input Low Current PCLK0, PCLK1 V CC = 2.625V, VIN = 0V -10 µA nPCLK0, nPCLK1 V CC = 2.625V, VIN = 0V -150 µA VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1 1.2 VCC V VOH Output High Voltage; NOTE 2 VCC – 1.4 VCC – 0.9 V VOL Output Low Voltage; NOTE2 VCC – 2.0 VCC – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 6 ©2012 Integrated Device Technology, Inc. Table 5H. LVDS DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Table 5I.. LVDS DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typi cal Maximum Units VOD Differential Output Voltage SEL_OUT = 0 247 454 mV VOD VOD Magnitude Change SEL_OUT = 0 50 mV VOS Offset Voltage SEL_OUT = 0 1.10 1.40 V VOS VOS Magnitude Change SEL_OUT = 0 50 mV Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage SEL_OUT = 0 247 454 mV VOD VOD Magnitude Change SEL_OUT = 0 50 mV VOS Offset Voltage SEL_OUT = 0 1.10 1.40 V VOS VOS Magnitude Change SEL_OUT = 0 50 mV
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 7 ©2012 Integrated Device Technology, Inc. Table 6A. LVPECL AC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters are measured at fOUT 1.5GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points. NOTE 5: Qx, nQx outputs measured differentially. Refer to Parameter Measurement Information Section for MUX Isolation diagram. Table 6B. LVPECL AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters are measured at fOUT 1.5GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points. NOTE 5: Qx, nQx outputs measured differentially. Refer to Parameter Measurement Information Section for MUX Isolation diagram. Symbol Parameter Test Conditions Minimum Typical Maximum Units f OUT Output Frequency 3G H z tPD Propagation Delay; NOTE 1 400 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz – 20MHz 0.22 0.28 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 20% to 80% 50 245 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation; NOTE 5 ƒOUT < 1.2GHz 45 dB Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 3G H z tPD Propagation Delay; NOTE 1 400 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz – 20MHz 0.22 0.28 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps t R / tF Output Rise/Fall Time 20% to 80% 50 235 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation; NOTE 5 ƒOUT < 1.2GHz 45 dB
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 8 ©2012 Integrated Device Technology, Inc. Table 6C. LVDS AC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters are measured at fOUT 1.5GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points. NOTE 5: Qx, nQx outputs measured differentially. Refer to Parameter Measurement Information Section for MUX Isolation diagram. Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters are measured at fOUT 1.5GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing point. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of input on each device, the output is measured at the differential cross points. NOTE 5: Qx, nQx outputs measured differentially. Refer to Parameter Measurement Information Section for MUX Isolation diagram. Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 3G H z tPD Propagation Delay; NOTE 1 400 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz – 20MHz 0.26 0.30 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 20% to 80% 50 200 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation; NOTE 5 ƒOUT < 1.2GHz 45 dB Symbol Parameter Test Conditions Minimum Typical Maximum Units fOUT Output Frequency 3G H z tPD Propagation Delay; NOTE 1 400 800 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 100MHz, Integration Range: 12kHz – 20MHz 0.26 0.31 ps tsk(o) Output Skew; NOTE 2, 3 25 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 20% to 80% 50 200 ps odc Output Duty Cycle 46 54 % MUXISOLATION MUX Isolation; NOTE 5 ƒOUT < 1.2GHz 45 dB
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 9 ©2012 Integrated Device Technology, Inc. Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Measured using a Rohde & Schwarz SMA100 as the input source. Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.22ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 10 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVPECL Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit Differential Input Level 2.5V LVPECL Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit Propagation Delay SCOPE Qx nQx VEE VCC, VCC_TAP -1.3V±0.165V SCOPE Qx nQx LVDS 3.3V±5% POWER SUPPL Y +–Float GND VCC V CMR Cross PointsVPP VCC VEE nPCLK[0:1] PCLK[0:1] SCOPE Qx nQx VEE VCC, VCC_TAP -0.5V±0.125V SCOPE Qx nQx 2.5V±5% POWER SUPPL Y +–Float GND VCC, VCC_TAP tPD nQ0, nQ1 Q0, Q1 nPCLK[0:1] PCLK[0:1]
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 11 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Skew LVPECL Output Rise/Fall Time Output Duty Cycle/Pulse Width/Period Part-to-Part Skew LVDS Output Rise/Fall Time MUX Isolation nQx Qx nQy Qy t sk(o) 20% 80% 80% 20% tR tF VSWING nQ0, nQ1 Q0, Q1 tPW tPERIOD tPW tPERIOD odc = x 100% nQ0, nQ1 Q0, Q1 t sk(pp) Part 1 Part 2 nQx Qx nQy Qy 20% 80% 80% 20% tR tF VOD nQ0, nQ1 Q0, Q1Amplitude (dB) Spectrum of Output Signal Q MUX_ISOL = A0 – A1 (fundamental) Frequencyƒ MUX selects static input MUX selects active input clock signal
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 12 ©2012 Integrated Device Technology, Inc. Parameter Measurement Information, continued Differential Output Voltage Setup Offset Voltage Setup 100 out out LVDSDC Input VOD/Δ VOD VDD out out LVDSDC Input ➤ VOS/Δ VOS VDD
ICS859S0212BGI REVISION A JUNE 4, 2012 18 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS859S0212I. Equations and example calculations are also provided. The total power dissipation for the ICS859S0212I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VCC_MAX * IEE_MAX = 3.465V * 55mA = 190.575mW
- Power (outputs) MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 190.575mW + 60mW = 250.575mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.251W * 92°C/W = 108.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 7. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
ICS859S0212BGI REVISION A JUNE 4, 2012 19 ©2012 Integrated Device Technology, Inc.
- Calculations and Equations.
The purpose of this section is to calculate power dissipation on the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination
- For logic high, V OUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V
- For logic low, V OUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW VOUT VCC VCC - 2V RL 50Ω
ICS859S0212BGI REVISION A JUNE 4, 2012 20 ©2012 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS859S0212I. Equations and example calculations are also provided. The total power dissipation for the ICS859S0212I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
- Power (core) MAX = VCC_MAX * ICC_MAX = 3.465V * 80mA = 277.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.277W * 92°C/W = 110.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 8. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
ICS859S0212BGI REVISION A JUNE 4, 2012 21 ©2012 Integrated Device Technology, Inc. Table 9. JA vs. Air Flow Table for a 16 Lead TSSOP
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER ICS859S0212BGI REVISION A JUNE 4, 2012 22 ©2012 Integrated Device Technology, Inc.
Ordering Information
Table 11. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS859S0212I Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specif ications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.
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