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Technical content
Features
- Two differential CML outputs
- IN/nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Maximum output frequency: 2GHz
- Output skew: 25ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Additive phase jitter, RMS: 0.042ps (typical)
- Propagation delay: 525ps (maximum)
- Operating voltage supply range: V CC = 2.375V to 3.63V, VEE = 0V
- -40°C to 85°C ambient operating temperature
- Available in lead-free (RoHS 6) package ICS858S011I 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View Pin AssignmentBlock Diagram nQ0 nQ IN nIN VREF_AC VT RIN RIN 5 6 7 8 16 15 14 13 IN VT VREF_AC nIN nQ0 nQ1 VCC VEE VEE VCC VEE VEE Vcc VCC Low Skew, 1-To-2, Differential-To-CML Fanout Buffer ICS858S011I Datasheet
Table 1. Pin Descriptions NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. extended periods may affect product reliability. 1 IN Input Non-inverting differential LVPECL clock input. 3V REF_AC Output Reference voltage for AC-coupled applications. 4 nIN Input Inverting differential LVPECL clock input. 5, 8, 13, 16 V CC Power Power supply pins. 6, 7, 14, 15 V EE Power Negative supply pins. 9, 10 Q1, nQ1 Output Differential output pair. CML interface levels. 11, 12 nQ0, Q0 Output Differential output pair. CML interface levels.
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram. NOTE 1: Outputs terminated with 50 to VCC. Table 3. AC Characteristics, VCC = 2.375V to 3.63V, VEE = 0V, TA = -40°C to 85°C has been reached under these conditions. All parameters characterized at 1.2GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage, same temperature, same frequency and with equal load conditions. Measured at the output differential cross points. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
4© Integrated Device Technology, Inc. September 19, 2017 ICS858S011I Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator “Rohde & Schwarz SMA100A Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator”. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.042ps (typical)
5© Integrated Device Technology, Inc. September 19, 2017 ICS858S011I Datasheet Parameter Measurement Information CML Output Load AC Test Circuit Part-to-Part Skew Single-ended & Differential Input Voltage Swing Differential Input Level Output Skew Propagation Delay SCOPE Qx Power Supply VEE VCC CML Driver -2.375V to -3.63V t sk(pp) Part 1 Part 2 Qx nQx Qy nQy VIN, VOUT 400mV (typical) VDIFF_IN, VDIFF_OUT 800mV (typical) V IH Cross Points VIN V IL IN nIN VCC VEE Qx nQx Qy nQy tPD nQ0, nQ1 Q0, Q1 IN nIN
6© Integrated Device Technology, Inc. September 19, 2017 ICS858S011I Datasheet Parameter Measurement Information, continued Output Rise/Fall Time Applications Information Recommendations for Unused Output Pins Outputs: CML Outputs All unused CML outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. nQ0, nQ1 Q0, Q1
and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
This section provides information on power dissipation and junction temperature for the ICS858S011I. Equations and example calculations are also provided. The total power dissipation for the ICS858S011I is the sum of the core power plus the power dissipation in the load(s). DD = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
- Power (core) MAX = VDD_MAX * IDD = 3.63V * 57mA = 206.9mW
- Power Dissipation for internal termination R T Power (RT)MAX = 4 * (VIN_MAX)2 / RT_MIN = (1.2V)2 / 80 = 72mW Total Power_MAX = 206.9mW + 72mW = 278.9mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 4. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection Table 5. JA vs. Air Flow Table for a 16 Lead VFQFN
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the righ t to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their o wn risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the U nited States and other countries. Other trademarks used herein are the property of Tech Support www.IDT.com/go/support Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Corporate Headquarters
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San Jose, CA 95138 USA www.IDT.com 12© Integrated Device Technology, Inc. September 19, 2017 ICS858S011I Datasheet Package Outline Drawings The package outline drawings are located in the last section of this document. The package information is the most current data available and is subject to change without notice or revision of this document.
Ordering Information
Table 7. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History
Part/Order Number Marking Package Shipping Packaging Temperature 858S011AKILF 011A “Lead-Free” 16 Lead VFQFN Tube -40 C to 85C 858S011AKILFT 011A “Lead-Free” 16 Lead VFQFN 2500 Tape & Reel -40 C to 85C Revision Date Description of Change September 19, 2017 Updated the package outline drawings; however, no mechanical changes Completed other minor improvements October 12, 2010 Initial release.