855S54 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: IDT
  • PDF pages: 19

Technical content

Features

  • Three differential LVDS output pairs
  • Three differential LVPECL clock input pairs
  • PCLKx pair can accept the following differential input levels: LVPECL and LVDS
  • Maximum output frequency: 2.5GHz
  • Additive phase jitter, RMS: 0.035ps (typical)
  • Propagation delay: 450ps (maximum)
  • Part-to-part skew: 200ps (maximum)
  • Full 2.5V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package 5 6 7 8 16 15 14 13 QB0 nQB0 QB1 nQB1 PCLKA0 nPCLKA0 PCLKA1 nPCLKA1 PCLKB nPCLKB CLK_SELB GND nQA CLK_SELA VDD QA CLK_SELA PCLKA0 nPCLKA0 PCLKA1 nPCLKA1 PCLKB nPCLKB CLK_SELB QA nQA QB0 nQB0 QB1 nQB1 Pulldown Pulldown Pullup/Pulldown Pulldown Pullup/Pulldown Pulldown Pullup/Pulldown Pulldown 855S54 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View Block Diagram Pin Assignment Dual 2:1 and 1:2 Differential-to-LVDS Multiplexer 855S54 Datasheet

Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 QB0, nQB0 Output Differential output pair. LVDS interface levels. 3, 4 QB1, nQB1 Output Differential output pair. LVDS interface levels. 5 PCLKB Input Pulldown Non-inverting LVPECL differential clock input. DD/2 default when left floating. LOW, selects QB0, nQB0 outputs. See Table 3B. LVCMOS/LVTTL interface levels. 8 GND Power Power supply ground. Pulldown Inverting differential LVPECL clock input. VDD/2 default when left floating. 10 PCLKA1 Input Pulldown Non-inverting LVPECL differential clock input. Pulldown Inverting differential LVPECL clock input. VDD/2 default when left floating. 12 PCLKA0 Input Pulldown Non-inverting LVPECL differential clock input. 13 V DD Power Positive supply pin.

14 CLK_SELA Input Pulldown

Clock select pin for PCLKA inputs. When HIGH, selects PCLKA1/nPCLKA1 inputs. When LOW, selects PCLKA0/nPCLKA0 inputs. See Table 3A. LVCMOS/LVTTL interface levels. 15, 16 nQA, QA Output Differential out put pair. LVDS interface levels.

1 Selects PCLKA1, nPCLKA1

1 Logic Low Follows PCLKB input

3©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 74.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C Symbol Parameter Test Conditio ns Minimum Typi cal Maximum Units VDD Positive Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 100 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 1.7 V DD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current CLK_SELA, CLK_SELB VDD = VIN = 2.625V 150 µA IIL Input Low Current CLK_SELA, CLK_SELB VDD = 2.625V, VIN = 0V -10 µA

4©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Table 4C. DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE: Refer to Parameter Measurement Information, 2.5V Output Load Test Circuit diagram. Symbol Parameter -40°C 25°C 85°C UnitsMin Typ Max Min Typ Max Min Typ Max IIH Input High Current PCLKAx, PCLKB nPCLKx, nPCLKB 150 150 150 µA I IL Input Low Current nPCLKAx, nPCLKB PCLKAx, PCLKB -150 -150 -150 µA V PP Peak-to-Peak Input Voltage; VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 V DD 1.2 V DD 1.2 V DD V Symbol Parameter -40°C 25°C 85°C UnitsMin Typ Max Min Typ Max Min Typ Max VOD Differential Output Voltage 750 1000 1250 750 1000 1320 750 1000 1370 mV VOD VOD Magnitude Change 30 50 30 50 30 50 mV VOUT Single-ended Output Voltage Swing 375 500 625 375 500 660 375 500 685 mV VOS VOS Magnitude Change 10 50 10 50 10 50 mV

Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C equilibrium has been reached under these conditions. NOTE: All parameters measured at  1.0GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured using clock input at 622.08MHz. and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Q/nQ output measured differentially. See Parameter Measurement Information for MUX Isolation diagram.

6©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator “IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator”. SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz) Additive Phase Jitter @ 622.08MHz 12kHz to 20MHz = 0.035ps (typical)

7©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Parameter Measurement Information LVDS Output Load AC Test Circuit Part-to-Part Skew Output Rise/Fall Time Differential Input Level MUX Isolation Propagation Delay VDD t sk(pp) Part 1 Part 2 Qx nQx Qy nQy 20% 80% 80% 20% tR tF VOD QA, QBx nQA, nQBx nPCLKA[0:1], nPCLKB PCLKA[0:1], PCLKB VDD GND VCMR Cross Points VPP Amplitude (dB) Spectrum of Output Signal Q MUX_ISOL = A0 – A1 (fundamental) Frequencyƒ MUX selects static input MUX selects active input clock signal tPD nQA, nQBx QA, QBx nPCLKA[0:1], nPCLKB PCLKA[0:1], PCLKB

8©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Offset Voltage Setup Differential Output Voltage Setup QA, QBx nQA, nQBx

11©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet A Typical Application for the 855S54 Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP Module. Problem Addressed: How to map the 2 Tx/Rx pairs of the multi-rate PHY to the single Tx/Rx pair on the SFP Module. Mode 1, 100BaseX Connected to SFP All lines are differential pairs, but drawn as single-ended to simplify the drawing. Bold red lines are active connections highlighting the signal path. MULTI-RATE PHY SFP M ODULE 100BaseFX 1000BaseX Tx Rx RxRx TxTx ? MULTI-RATE PHY SFP M ODULE 100BaseFX 1000BaseX Tx Rx Tx Rx Rx Tx ICS855S54I CLK_SELA = 0 PCLKA1 QB0 QB1 PCLKA0 CLK_SELB = 0 QA PCLKB

12©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Mode 2, 100BaseX Connected to SFP All lines are differential pairs, but drawn as single-ended to simplify the drawing. Bold red lines are active connections highlighting the signal path. MULTI-RATE PHY SFP M ODULE 100BaseFX 1000BaseX Tx Rx Tx Rx Rx Tx ICS855S54I CLK_SELA = 1 PCLKA1 QB0 QB1 PCLKA0 CLK_SELB = 1 QA PCLKB

and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

This section provides information on power dissipation and junction temperature for the 855S54. Equations and example calculations are also provided. The total power dissipation for the 855S54 is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

  • Power (core) MAX = VDD_MAX * IDD_MAX = 2.625V * 100mA = 262.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN This device is pin and function compatible and a suggested replacement for 855S54.

16©2017 Integrated Device Technology, Inc. September 19, 2017 855S54 Datasheet Package Outline Drawings The package outline drawings are located in the last section of this document. The package information is the most current data available and is subject to change without notice or revision of this document.

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Revision History

Part/Order Number Marking Package Shipping Packaging Temperature 855S54AKILF 554A “Lead-Free” 16 Lead VFQFN Tube -40C to 85C 855S54AKILFT 554A “Lead-Free” 16 Lead VFQFN Tape & Reel -40C to 85C Revision Date Description of Change September 19, 2017 Updated the package outline drawings; however, no mechanical changes Completed other minor improvements February 10, 2016 General Description - deleted HiperClocks logo. Ordering Information Table - deleted count for Tape & Reel. Deleted “ICS” prefix and “I” suffix in the part number throughout the datasheet.

+ 3.10 2.90 Q 0.10 C 1.80 1.60 TOP VIEW Llill1.60 8 X 0.50 1 6 -X0.30 8 X j 0.20 BOTTOM VIEW NOTES: NL/NLG16P2, PSC-4169-02, Rev 03, Page 1 vi Io.101 c 1

0.70 BSC

SEATING PLANEQJL lolo.oslcl 0.00 SIDE VIEW 1. ALL DIMENSIONS ARE IN mm.ANGLES IN DEGREES © 2019 Renesas Electronics Corporation

3.30 2.20 C0.35 NL/NLG16P2, PSC-4169-02, Rev 03, Page 2 0.55 1.70

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