8543AG-09LF | DigiCamel IC Datasheet

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Features

Four differential LVDS output pairs Selectable differential CLK, nCLK or LVPECL clock inputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL Maximum output frequency: 800MHz Translates any single-ended input signal to LVDS levels with resistor bias on nCLK input Additive phase jitter, RMS: 0.146ps (typical) Output skew: 100ps (maximum) Part-to-part skew: 700ps (maximum) Propagation delay: 3.3ns (maximum) Full 3.3V supply mode 0°C to 70°C ambient operating temperature Available in lead-free (RoHS 6) package Industrial temperature information available upon request HiPerClockS™ ICS ICS8543-09 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram D Q LE nQ0 nQ1 nQ2 nQ3 CLK_EN PCLK nPCLK CLK_SEL OE Pulldown Pulldown Pullup Pullup Pullup Pullup CLK nCLK Pulldown GND OE nPCLK PCLK nCLK CLK CLK_SEL CLK_EN GND VDD nQ0 VDD nQ1 nQ2 GND nQ3

ICS8543AG-09 REVISION A JANUARY 15, 2010 2 ©2010 Integrated Device Technology, Inc. Table 1. Pin Descriptions Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 9, 13 GND Power Power supply ground.

2 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects PCLK/nPCLK inputs. When LOW, selects CLK/nCLK input. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup Inverting differential clock input. 6 PCLK Input Pulldown Non-inverting differential LVPECL clock input. 7 nPCLK Input Pullup Inverti ng differential LVPECL clock input. Q3/nQ3. LVCMOS/LVTTL interface levels. 10, 18 V DD Power Positive supply pins. 11, 12 nQ3, Q3 Output Differential output pai r. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential output pai r. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential output pai r. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential output pai r. LVDS interface levels.

ICS8543AG-09 REVISION A JANUARY 15, 2010 3 ©2010 Integrated Device Technology, Inc. In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B. Figure 1. CLK_EN Timing Diagram Wiring the Differential Input to Accept Single-Ended Levels.

0 X X Hi-Impedance Hi-Impedance

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

ICS8543-09 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543AG-09 REVISION A JANUARY 15, 2010 4 ©2010 Integrated Device Technology, Inc. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 91.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 50 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL V DD = VIN = 3.465V 150 µA OE, CLK_EN V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK_SEL V DD = 3.465V, VIN = 0V -5 µA OE, CLK_EN V DD = 3.465V, VIN = 0V -150 µA

ICS8543-09 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543AG-09 REVISION A JANUARY 15, 2010 5 ©2010 Integrated Device Technology, Inc. Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK V DD = VIN = 3.465V 150 µA nCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current CLK V DD = 3.465V, VIN = 0V -5 µA nCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 V DD – 0.85 V Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current PCLK V DD = VIN = 3.465V 150 µA nPCLK V DD = VIN = 3.465V 5 µA IIL Input Low Current PCLK V DD = 3.465V, VIN = 0V -5 µA nPCLK V DD = 3.465V, VIN = 0V -150 µA VPP Peak-to-Peak Input Voltage; NOTE 1 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1, 2 1.5 V DD V Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 200 280 360 mV ∆VOD VOD Magnitude Change 40 mV VOS Offset Voltage 1.125 1.25 1.375 V ∆VOS VOS Magnitude Change 5 25 mV IOz High Impedance Leakage -10 +10 µA IOFF Power Off Leakage -20 ±1 +20 µA IOSD Differential Output Short Circuit Current -3.5 -5 mA IOS Output Short Circuit Current -3.5 -5 mA

ICS8543AG-09 REVISION A JANUARY 15, 2010 6 ©2010 Integrated Device Technology, Inc. Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C has been reached under these conditions. NOTE: All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output crossing points. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

ICS8543-09 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543AG-09 REVISION A JANUARY 15, 2010 7 ©2010 Integrated Device Technology, Inc. Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.146ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

ICS8543-09 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543AG-09 REVISION A JANUARY 15, 2010 8 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information 3.3V LVDS Output Load AC Test Circuit Differential Input Level Part-to-Part Skew Differential Output Level Output Skew Propagation Delay SCOPE Qx nQx LVDS 3.3V±5% POWER SUPPL Y +– Float GND VDD VDD GND CLK, PCLK nCLK, nPCLK VOS Cross Points VOD nQx Qx nQy Qy tsk(pp) Part 1 Part 2 VDD GND nQ0:nQ3 Q0:Q3 V CMR Cross Points V PP tsk(o) nQx Qx nQy Qy nQ0:nQ3 Q0:Q3 CLK, PCLK nCLK, nPCLK tPD

ICS8543-09 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS8543AG-09 REVISION A JANUARY 15, 2010 9 ©2010 Integrated Device Technology, Inc. Parameter Measurement Information, continued Output Duty Cycle/Pulse Width/Period Offset Voltage Setup High Impedance Leakage Current Setup Output Rise/Fall Time Differential Output Voltage Setup Power Off Leakage Setup tPW tPERIOD tPW tPERIOD odc = x 100% nQ0:nQ3 Q0:Q3 out out LVDSDC Input ➤ VOS/∆ VOS VDD out out LVDSDC Input 3.3V±5% POWER SUPPL Y Float GND + _ IOZ IOZ 20% 80% 80% 20% tR tF VOD nQ0:nQ3 Q0:Q3 100 out out LVDSDC Input VOD/∆ VOD VDD LVDS IOFF VDD

ICS8543AG-09 REVISION A JANUARY 15, 2010 13 ©2010 Integrated Device Technology, Inc. additional protection, a 1kΩ resistor can be tied from CLK to ground. resistance is not required but can be added for additional protection. recommended to terminate the unused outputs. Figure 5. Typical LVDS Driver Termination

ICS8543AG-09 REVISION A JANUARY 15, 2010 14 ©2010 Integrated Device Technology, Inc. This section provides information on power dissipation and junction temperature for the ICS8543-09. Equations and example calculations are also provided. The total power dissipation for the ICS8543-09 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. wire and bond pad temperature remains below 125°C. a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below. Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. for use in life support devices or critical medical instruments.

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’ s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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Product Information

8543AG-09LF specifications and overview.

Summary

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Description

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer

Source title 8543AG-09LF Datasheet(PDF) - Integrated Device Technology

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