85411I IDT | Alldatasheet

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Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer 85411I Data Sheet ©2016 Integrated Device Technology, Inc Revision B January 20, 20161 GENERAL DESCRIPTION The 85411I is a low skew, high performance 1-to-2 Differential- to-LVDS Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The 85411I is characterized to operate from a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 85411I ideal for those clock distribution applications demanding well defi ned performance and repeatability.

FEATURES

  • Two differential LVDS outputs
  • One differential CLK, nCLK clock input
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 650MHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input
  • Output skew: 25ps (maximum)
  • Part-to-part skew: 300ps (maximum)
  • Additive phase jitter, RMS: 0.05ps (typical)
  • Propagation delay: 2.5ns (maximum)
  • 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead free (RoHS 6) package BLOCK DIAGRAM P IN ASSIGNMENT 85411I 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View nQ0 nQ1 VDD CLK nCLK GND nQ0 nQ1 CLK nCLK

TABLE 1. PIN DESCRIPTIONS TABLE 2. PIN CHARACTERISTICS 1, 2 Q0, nQ0 Output Differential output pair. LVDS interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5 GND Power Power supply ground. 6 nCLK Input Pulldown Inverting differential clock input. 7 CLK Input Pullup Non-inverting differential clock input. Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

©2016 Integrated Device Technology, Inc Revision B January 20, 20163 TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V DD TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, V DD Symbol Parameter Test Conditions Minimum Typical Maximum Units V DD Positive Supply Voltage 2.97 3.3 3.63 V I DD Power Supply Current 50 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units I IH Input High Current CLK V DD = V IN = 3.63V 5 µA nCLK V DD = V IN = 3.63V 150 µA I IL Input Low Current CLK V DD = 3.63, V IN = 0V -150 µA nCLK V DD = 3.63V, V IN = 0V -5 µA V PP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V V CMR Common Mode Input Voltage; NOTE 1, 2 0.5 V DD - 0.85 V NOTE 1: V IL should not be less than -0.3V. NOTE 2: Common mode voltage is defi ned as V IH NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifi cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. TABLE 3C. LVDS DC CHARACTERISTICS, V DD ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Inputs, V I -0.5V to V DD + 0.5V Outputs, I O Continuous Current 10mA Surge Current 15mA Package Thermal Impedance, θ JA 112.7°C/W (0 lfpm) Storage Temperature, T STG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V OD Differential Output Voltage 247 325 454 mV ∆ V OD VOD Magnitude Change 0 50 mV V OS Offset Voltage 1.325 1.45 1.575 V ∆ V OS VOS Magnitude Change 5 50 mV I OFF Power Off Leakage -20 ±1 +20 µA I OSD Differential Output Short Circuit Current -3.5 -5 mA I OS Output Short Circuit Current -3.5 -5 mA

TABLE 4. AC CHARACTERISTICS, V specifi cations after thermal equilibrium has been reached under these conditions. All parameters measured at ƒ ≤ 650MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. at the differential cross points. NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.

©2016 Integrated Device Technology, Inc Revision B January 20, 20165 ADDITIVE PHASE JITTER Input/Output Additive Phase Jit- ter @ 200MHz (12kHz to 20MHz) = 0.05ps typical -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M The spectral purity in a band at a specifi c offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specifi ed plot in many applications. Phase noise is defi ned as the ratio of the noise power present in a 1Hz band at a specifi ed offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels As with most timing specifi cations, phase noise measurements has issues relating to the limitations of the equipment. Often the noise fl oor of the equipment is higher than the noise fl oor of the device. (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specifi ed, the phase noise is called a dBc value, which simply means dBm at a specifi ed offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. This is illustrated above. The device meets the noise fl oor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. OFFSET FROM CARRIER FREQUENCY (HZ) SSB PHASE NOISE dBc/HZ

©2016 Integrated Device Technology, Inc Revision B January 20, 20166 PARAMETER MEASUREMENT INFORMATION DIFFERENTIAL INPUT LEVEL3.3V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW PROPAGATION DELAY OUTPUT RISE/FALL TIME OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL OUTPUT VOLTAGE SETUP

©2016 Integrated Device Technology, Inc Revision B January 20, 20167 POWER OFF LEAKAGE SETUPOFFSET VOLTAGE SETUP OUTPUT SHORT CIRCUIT CURRENT SETUP DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP PARAMETER MEASUREMENT INFORMATION, CONTINUED

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

This section provides information on power dissipation and junction temperature for the85411I. Equations and example calculations are also provided. The total power dissipation for the85411I is the sum of the core power plus the power dissipated in the load(s). = 3.3V + 10% = 3.63V, which gives worst case results.

  • Power (core) MAX = V DD_MAX * I DD_MAX = 3.63V * 50mA = 181.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air fl ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow, and the type of board (multi-layer).

TABLE 5. THERMAL RESISTANCE θ JA FOR 8-LEAD SOIC, FORCED CONVECTION NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 6. θ NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 8. ORDERING INFORMATION

©2016 Integrated Device Technology, Inc Revision B January 20, 201614 REVISION HISTORY SHEET Rev Table Page Description of Change Date B T3C 3 Changed V DD from ±5% to ±10% throughout datasheet. LVDS DC Characteristics Table - changed V OD range from 200mV min./360mV max. to 247mV min./454mV max. Changed ∆ V OD from 40mV max. to 50mV max. Changed V OS Changed ∆ V OS from 25mV max. to 50mV max. Added Recommendations for Unused Output Pins. Added Power Considerations. 9/25/06 B 3x, 4 3, 4 Corrected temperature in tables. 11/7/07 B T3C 3 LVDS DC Characteristics Table - deleted V OH & V OL rows. 1/20/09 B T8 Removed ICS from the part number where needed. General Description - Removed ICS Chip and HiPerClockS. Features section - removed reference to leaded packages. Ordering Information - removed quantity from tape and reel. Deleted the LF note below the table. Updated header and footer. 1/20/16

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifi cations described herein at any time, without notice, at IDT's sole discretion. Performance specifi cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect- ed to signifi cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type defi nitions and a glossary of common terms, visit www.idt.com/go/glossary. Copyright ©2016 Integrated Device Technology, Inc. All rights reserved. Corporate Headquarters

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