854110AKILF

ICS854110I IDT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• Two differential input reference clocks
• Differential pair can accept the following differential input levels: LVPECL, LVDS
• Ten LVDS outputs
• Maximum clock frequency: 200MHz
• Output slew rate control
• Fail-safe differential inputs
• LVCMOS interface levels for all control inputs
• Output skew: 260ps (maximum), for fastest slew rate setting of

0.650 V/ns

• Part-to-part skew: 1.2ns (maximum)
• Full 2.5V supply voltage
• Lead-free (RoHS 6) 32-Lead VFQFN and 32-Lead LQFP package
• -40°C to 85°C ambient operating temperature 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ISET CLK_SEL CLK0 nCLK0 GND CLK1 nCLK1 nOE nQ3 nQ4 nQ5 nQ6 GND nQ9 nQ8 nQ7 VDD nQ0 nQ1 nQ2 GND VDD 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ISET CLK_SEL CLK0 nCLK0 GND CLK1 nCLK1 nOE nQ3 nQ4 nQ5 nQ6 GND nQ9 nQ8 nQ7 VDD nQ0 nQ1 nQ2 GND VDD fREF CLK0 nCLK0 CLK1 nCLK1 CLK_SEL ISET nOE Pulldown nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 Slew-Rate Control RSET Pulldown GND Block Diagram Pin Assignments 854110AKI 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K package Top View 854110AYI 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View

ICS854110AKI REVISION B JANUARY 27, 2011 2 ©2011 Integrated Device Technology, Inc. Table 1. Pin Descriptions NOTE: Pulldown refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics

1 ISET

reference current for setting the slew rate of the differential outputs Q[0:9], nQ[0:9]. 2 CLK_SEL Input Pulldown Input clock select. See Table 3A for function. LVCMOS/LVTTL interface levels. 3 CLK0 Input Non-inverting clock/data input 0. 4 nCLK0 Input Inverting differential clock input 0. 5, 9, 25 GND Power Power supply ground. 6 CLK1 Input Non-inverting clock/data input 1. 7 nCLK1 Input Inverting differential clock input 1. 8 nOE Input Pulldown Output enable. See Table 3B for function. LVCMOS/LVTTL interface levels. 10, 11 nQ9, Q9 Output Differential output pair 9. LVDS interface levels. 12, 13 nQ8, Q8 Output Differential output pair 8. LVDS interface levels. 14, 15 nQ7, Q7 Output Differential output pair 7. LVDS interface levels. 16, 32 V DD Power Power supply pins. 17, 18 nQ6, Q6 Output Differential output pair 6. LVDS interface levels. 19, 20 nQ5, Q5 Output Differential output pair 5. LVDS interface levels. 21, 22 nQ4, Q4 Output Differential output pair 4. LVDS interface levels. 23, 24 nQ3, Q3 Output Differential output pair 3. LVDS interface levels. 26, 27 nQ2, Q2 Output Differential output pair 2. LVDS interface levels. 28, 29 nQ1, Q1 Output Differential output pair 1. LVDS interface levels. 30, 31 nQ0, Q0 Output Differential output pair 0. LVDS interface levels.

ICS854110AKI REVISION B JANUARY 27, 2011 3 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Function Tables Table 3A. CLK_SEL Configuration Table NOTE: CLK_SEL is an asynchronous control. Table 3B. nOE Configuration Table NOTE: OE is an asynchronous control. Table 3C. RSET Configuration Table NOTE: The RSET resistor at the ISET pin allows configuration of the outputs to one of four pre-set output slew rates. A 5% variation of the RSET resistor size will be tolerated. NOTE: Slew rates are defined as ±100mV from the center of Q – nQ signal. Table 3D. Guaranteed Input Fail Safe Operations for CLK0, nCLK0 and CLK1, nCLK1 Input OperationCLK_SEL

0 CLK0, nCLK0 is the selected reference clock

1 CLK1, nCLK1 is the selected reference clock

0 Outputs Qx, nQx are enabled. 1 Outputs Qx, nQx are in high-impedance state. RSET Typical Output Slew Rate (V/ns)Resistor Size (kΩ) 4 0.650 (fastest) 15 0.170 50 0.150 150 0.115 (slowest) Input State of Selected Input Outputs Q[0:9], nQ[0:9] Logic Low (Selected Input: CLKx = LOW, nCLKx = HIGH) Logic Low (Qx = LOW, nQx = HIGH) Logic High (Selected Input: CLKx = HIGH, nCLKx = LOW) Logic High (Qx = HIGH, nQx = LOW) Inputs Open (Selected Input: CLKx = open, nCLKx = open) Logic High (Qx = HIGH, nQx = LOW) Inputs Shorted (Selected Input: CLKx shorted to nCLKx and tied to VDD) Logic High (Qx = HIGH, nQx = LOW) Input Shorted (Selected Input: CLKx shorted to nCLKx and floating) Logic High (Qx = HIGH, nQx = LOW)

ICS854110AKI REVISION B JANUARY 27, 2011 4 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Table 4C. Differential DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θ JA

32 Lead VFQFN

32 Lead LQFP

37.0°C/W (0 mps) 65.7°C/W (0 mps) Storage Temperature, T STG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current No Load, RSET not connected 18 mA All Outputs Loaded, RSET = 4kΩ 86 mA No Load, RSET = 4kΩ 30 mA Symbol Parameter Test Conditio ns Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current CLK_SEL, nOE V DD = VIN = 2.625V 150 µA IIL Input Low Current CLK_SEL, nOE V DD = 2.625V, VIN = 0V -5 µA Symbol Parameter Test Conditi ons Minimum Typical Maximum Units VPP Peak-to-Peak Input Voltage; NOTE 1 0.15 1.2 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.8 V DD - 0.85 V

ICS854110AKI REVISION B JANUARY 27, 2011 5 ©2011 Integrated Device Technology, Inc. Table 5. AC Electrical Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C

ICS854110AKI REVISION B JANUARY 27, 2011 6 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: Input Duty Cycle must be 50%. t R / tF Output Rise/ Fall Time; 30% to 70% RSET = 4kΩ 100 300 500 ps RSET = 15kΩ 600 1030 1600 ps RSET = 50kΩ 650 1160 1850 ps RSET = 150kΩ 800 1540 2200 ps Symbol Parameter Test Conditio ns Minimum Typical Maximum Units

ICS854110AKI REVISION B JANUARY 27, 2011 7 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator used is, "Rohde & Schwarz SMA 100A Signal Generator into a HP 8133A 3GHz Pulse Generator". Additive Phase Jitter @ 125MHz 12kHz to 20MHz = 0.291ps (typical) SSB Phase Noise dBc/Hz Offset from Carrier Frequency (Hz)

ICS854110AKI REVISION B JANUARY 27, 2011 8 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Parameter Measurement Information 2.5V LVDS Output Load AC Test Circuit Output Skew Pulse Skew Differential Input Level Part-to-Part Skew Propagation Delay SCOPE Qx nQx LVDS 2.5V±5% POWER SUPPL Y +– Float GND VDD tsk(o) Qx nQx Qy nQy tPLH tPHL tSK(p) = |tPHL - tPLH| CLK[0:1] nCLK[0:1] Qy nQy VDD nCLK0, nCLK1 CLK0, CLK1 GND VCMR Cross Points VPP tsk(pp) Part 1 Part 2 Qx nQx Qy nQy tPD nQ[0:9] Q[0:9] nCLK[0:1] CLK[0:1]

ICS854110AKI REVISION B JANUARY 27, 2011 9 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Parameter Measurement Information, continued Output Rise/Fall Time Differential Output Voltage Setup Differential Output Slew Rate Output Duty Cycle/Pulse Width/Period Offset Voltage Setup 30% 70% 70% 30% tR tF VOD nQ[0:9] Q[0:9] 100 out out LVDSDC Input VOD/∆ VOD VDD Q – nQ tR tF VFVR -100mV +100mV +100mV -100mV 50% nQ[0:9] Q[0:9] tPW tPERIOD tPW tPERIOD odc = x 100% out out LVDSDC Input ➤ VOS/∆ VOS VDD

ICS854110AKI REVISION B JANUARY 27, 2011 12 ©2011 Integrated Device Technology, Inc. and the inner edges of pad pattern for the leads to avoid any shorts. Electrically Enhance Leadframe Base Package, Amkor Technology. Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS854110AKI REVISION B JANUARY 27, 2011 13 ©2011 Integrated Device Technology, Inc. at the receiver and a 100Ω differential transmission line environment. Figure 4. Typical LVDS Driver Termination

ICS854110AKI REVISION B JANUARY 27, 2011 14 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS854110I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS54110I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. Total power dissipation, includes power dissipation on external components.  P_core+load = V DD_MAX * IDD_core+load = 2.625V * 86mA = 225.75mW Where: IDD_core+load is the total supply current which includes external components To calculate the power dissipation on the device alone, Pd_total, and use it for junction temperature calculation, subtract the power dissipation on the external components.  Pd_total = P_core+load – (P_load + P_rset) Where: P_load is power dissipation on the output loadings P_rset is power dissipation on the R SET The load current per output is: I o u t = ( IDD_core+load – IDD_no_load) / N = (86mA – 18mA) / 10 = 6.8mA Where: IDD_no_load is IDD current at no load condition N is number of outputs Power Dissipation on output loads  P_load = (Iout)^2 * R_load * N = (6.8mA)^2 * 100 Ω * 10 = 46.2mW Power Dissipation on RSET  P_rset = (Vrset)^2 / R SET = (1V)^2 / 4kΩ = 0.25mW (NOTE: P_rset is small and can be negligible) Total Power Dissipation on the part excluding the power dissipation on the external components. Pd_total = P_core+load – (P_load + P_rset) = 179.3mW

ICS854110AKI REVISION B JANUARY 27, 2011 15 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 65.7°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6A. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection Table 6B. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W θJA by Velocity Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W

ICS854110AKI REVISION B JANUARY 27, 2011 16 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Reliability Information Table 7A. θJA vs. Air Flow Table for a 32-Lead VFQFN Table 7B. θJA vs. Air Flow Table for a 32-Lead LQFP Transistor Count The transistor count for ICS854110I is: 1757 θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29.0°C/W θJA vs. Air Flow Meters per Second 01 2 . 5 Multi-Layer PCB, JEDEC Standard Test Boards 65.7°C/W 55.9°C/W 52.4°C/W

ICS854110AKI REVISION B JANUARY 27, 2011 17 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Package Outline and Package Dimensions Package Outline - K Suffix for 32-Lead VFQFN Table 8A. Package Dimensions for 32-Lead VFQFN Reference Document: JEDEC Publication 95, MO-220 NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8A. To p View Index Area D Chamfer 4x 0.6 x 0.6 max OPTIONAL Anvil Singulation A 0. 08 C C Seating Plane E2 E2 L (N -1)x e (Re f.) (Ref.) N & N Even N e (Ref.) N & N Odd e (Ty p.) If N & N are Even (N -1)x e (Re f.) b Th er mal Base N OR Anvil Singulation N-1N CHAMFER N-1 N RADIUS Bottom View w/Type C IDBottom View w/Type A ID There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 32 A 0.80 1.00 A1 00 . 0 5 A3 0.25 Ref. b 0.18 0.30 ND & NE 8 D & E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.50

ICS854110AKI REVISION B JANUARY 27, 2011 18 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Package Outline and Package Dimensions Package Outline - Y Suffix for 32-Lead LQFP Table 8B. Package Dimensions 32 Lead LQFP Reference Document: JEDEC Publication 95, MS-026 JEDEC Variation: BBA All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.45 c 0.09 0.20 D & E 9.00 Basic D1 & E1 7.00 Basic e 0.80 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10

ICS854110AKI REVISION B JANUARY 27, 2011 19 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER

Ordering Information

Table 9. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. devices or critical medical instruments.

ICS854110AKI REVISION B JANUARY 27, 2011 20 ©2011 Integrated Device Technology, Inc. ICS854110I Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER Revision History Sheet Rev Table Page Description of Change Date B T4A 4 Power Supply DC Characteristics Table - added I DD spec of 30mA max. 1/27/11

ICS854110I Preliminary Data Sheet 2.5V DIFFERENTIAL LVDS CLOCK BUFFER DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the ri ght to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is s ubject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. The informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2011. All rights reserved.

6024 Silver Creek Valley Road

San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 We’ve Got Your Timing Solution