ICS854104I IDT | Alldatasheet
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Four differential L VDS output pairs One differential clock input pair CLK/nCLK can accept the following differential input levels: L VPECL, L VDS, L VHSTL, HCSL, SSTL Each output has an individual OE control Maximum output frequency: 700MHz T ranslates differential input signals to L VDS levels Additive phase jitter, RMS: 0.232ps (typical) Output skew: 50ps (maximum) Part-to-part skew: 350ps (maximum) Propagation delay: 1.3ns (maximum) 3.3V operating supply -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) packaging Block Diagram Pin Assignment ICS854104 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package T op View nQ0 nQ1 nQ2 nQ3 CLK OE2 OE3 OE1 OE0 nCLK Pulldown Pullup/Pulldown Pullup Pullup Pullup Pullup nQ0 nQ1 nQ2 nQ3OE3 nCLK CLK GND VDD OE2 OE1 OE0
ICS854104AGI REVISION B JANUARY 30, 2014 2 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Pin Descriptions and Characteristics T able 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See T able 2,Pin Characteristics, for typical values. T able 2. Pin Characteristics Function Table T able 3. Output Enable Function T able Number Name Type Description 1 OE0 Input Pullup Output enable pin for Q0, nQ0 outputs. See Table 3. LVCMOS/LVTTL interface levels. 2 OE1 Input Pullup Output enable pin for Q1, nQ1 outputs. See Table 3. LVCMOS/LVTTL interface levels. 3 OE2 Input Pullup Output enable pin for Q2, nQ2 outputs. See Table 3. LVCMOS/LVTTL interface levels. 4V DD Power Positive supply pin. 5 GND Power Power supply ground. 6 CLK Input Pulldown Non-inverting differential clock input. 7 nCLK Input Pullup/Pulldown Inverting differential clock input. V DD/2 default when left floating. 8 OE3 Input Pullup Output enable pin for Q3, nQ3 outputs. See Table 3. LVCMOS/LVTTL interface levels. 9, 10 nQ3, Q3 Output Differential output pair. LVDS interface levels. 11, 12 nQ2, Q2 Output Differential output pair. LVDS interface levels. 13, 14 nQ1, Q1 Output Differential output pair. LVDS interface levels. 15, 16 nQ0, Q0 Output Differential output pair. LVDS interface levels. Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k Inputs Outputs
0 High-Impedance
1 Active (default)
ICS854104AGI REVISION B JANUARY 30, 2014 3 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only . Functional operation of he product at these conditions or any conditions beyond those listed in theDC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability . Table 4A. LVDS Power Supply DC Characteristics,VDD = 3.3V ± 5%, TA = -40°C to 85°C T able 4B. L VCMOS/L VTTL DC Characteristics,VDD = 3.3V ± 5%, TA = -40°C to 85°C T able 4C. Differential DC Characteristics,VDD = 3.3V ± 5%, TA = -40°C to 85°C NOTE 1: VIL should not be less than -0.3V . NOTE 2: Common mode input voltage is defined as VIH. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 100.3°C/W (0 mps) Storage Temperature, TSTG -65Ct o1 5 0C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Positive Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage 2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current V DD =V IN = 3.465V 5 µA IIL Input Low Current V DD = 3.465V , VIN = 0V -150 µA Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current CLK, nCLK V DD =V IN = 3.465V 150 µA IIL Input Low Current CLK V DD = 3.465V , VIN =0 V - 5 µ A nCLK V DD = 3.465V , VIN = 0V -150 µA VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 V DD – 0.85 V
ICS854104AGI REVISION B JANUARY 30, 2014 4 ©2014 Integrated Device Technology, Inc. Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C has been reached under these conditions. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. point of the input to the differential output crossing point. the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS854104AGI REVISION B JANUARY 30, 2014 5 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. The source generator is the Rhode & Schwarz SMA 100A Signal Generator 9kHz – 6GHz. Phase noise is measured with the Agilent E5052A Signal source Analyzer. Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.232ps (typical) SSB Phase Noise (dBc/Hz) Offset from Carrier Frequency (Hz)
ICS854104AGI REVISION B JANUARY 30, 2014 6 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information 3.3V L VDS Output Load AC Test Circuit Propagation Delay Output Skew Differential Input Level Part-to-Part Skew Output Duty Cycle/Pulse Width/Period VDD tPD Q[0:3] nQ[0:3] nCLK CLK Qx nQx Qy nQy VDD nCLK CLK GND V CMRCross PointsV PP t sk(pp) Par t 1 Par t 2 Qx nQx Qy nQy Q[0:3] nQ[0:3]
ICS854104AGI REVISION B JANUARY 30, 2014 7 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued Output Rise/Fall Time Differential Output V oltage Setup Offset V oltage Setup 20% 80% 80% 20% t R t F VOD Q[0:3] nQ[0:3]
ICS854104AGI REVISION B JANUARY 30, 2014 11 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS854104I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854104I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V , which gives worst case results. Power (core) MAX =V DD_MAX *I DD_MAX = 3.465V * 75mA = 259.875mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction T emperature JA = Junction-to-Ambient Thermal Resistance Pd_total = T otal Device Power Dissipation (example calculation is in section 1 above) TA = Ambient T emperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistanceJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 100.3°C/W per T able 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). T able 6. Thermal ResistanceJA for 16-Lead TSSOP , Forced Convection JA by Velocity Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W
ICS854104AGI REVISION B JANUARY 30, 2014 12 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Reliability Information Ta b l e 7 .JA vs. Air Flow T able for a 16-Lead TSSOP T ransistor Count The transistor count for ICS854104I is: 286 Package Outline and Package Dimensions Package Outline - G Suffix for 16-Lead TSSOP T able 8. Package Dimensions Reference Document: JEDEC Publication 95, MO-153 JA by Velocity Meters per Second 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0° 8° aaa 0.10
ICS854104AGI REVISION B JANUARY 30, 2014 13 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Ordering Information
T able 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 854104AGILF 54104AIL “Lead-Free” 16-Lead TSSOP T ube -40 Ct o8 5C 854104AGILFT 54104AIL “Lead-Free” 16-Lead TSSOP T ape & Reel -40 Ct o8 5C
ICS854104AGI REVISION B JANUARY 30, 2014 14 ©2014 Integrated Device Technology, Inc. ICS854104I DATA SHEET LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Revision History Sheet Rev T able Page Description of Change Date A T5 4 AC Characteristics - deleted "Bank A" test conditions from part-to-part skew row. 8/13/09 B T5 4 AC Characteristics - Additive Phase Jitter, added maximum spec for 155.52MHz and added 100MHz specs. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated L VDS Driver T ermination. 9/10/10 B T4B Corrected typo error; IIH = 5µA Max, IIL = -150µA Min. Deleted quantity from Tape & Reel 1/30/14
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